Advertisement

Abstract

The paper presents why power and timing can be improved by physical design automation where the cells are generated on the fly. The non-use of cell libraries allows the implementation of any logic function defined at logic synthesis, using simple gates or static CMOS complex gates – SCCG. The use of SCCG reduces the amount of transistor and helps to reduce wire length. It is discussed the main strategies in the automatic layout synthesis, like transistor topology, contacts and vias management, body ties placement, power lines management, routing management and transistor sizing. In both methodologies, standard cell and automatic layout, it is needed accurate pre-characterization tools. The development of efficient physical design automation is the key to find better solution than traditional standard cell methodologies.

Keywords

Physical Design Wire Length NMOS Transistor Layout Strategy Placement Algorithm 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. 1.
    SIA International Semiconductor Roadmap, Semiconductor Industry Association (2001) Google Scholar
  2. 2.
    Johann, M., Kindel, M., Reis, R.: Layout Synthesis Using Transparent Cells and FOTC Routing. In: 38th IEEE Midwest Symposium on Circuits and Systems, IEEE Circuits and Systems Society, Rio de Janeiro (1995)Google Scholar
  3. 3.
    Detjens, E., Gannot, G., Rudell, R., Sangiovanni-Vinccentelli, A.L., Wang, A.: Technology Mapping in MIS. In: Proceedings of ICCAD, pp. 116-119 (1987)Google Scholar
  4. 4.
    Reis, A., Robert, M., Auvergne, D., Reis, R.: Associating CMOS Transistors with BDD Arcs for Technology Mapping. Electronic Letters 31(14) (July 1995)Google Scholar
  5. 5.
    Reis, A., Reis, R., Robert, M., Auvergne, D.: Library Free Technology Mapping. In: VLSI: Integrated Systems on Silicon, pp. 303–314. Chapman-Hall, Boca Raton (1997)Google Scholar
  6. 6.
    Hentschke, R., Reis, R.: Pic-Plac: A Novel Constructive Algorithm for Placement. In: IEEE International Symposium on Circuits and Systems (2003)Google Scholar
  7. 7.
    Hentschke, R., Reis, R.: Improving Simulated Annealing Placement by Applying Random and Greedy Mixed Perturbations. In: Chip in Sampa, São Paulo, 16th Symposium on Integrated Circuits and Systems Design, IEEE Society Computer Press, Los Alamitos (2003)Google Scholar
  8. 8.
    Sherwani, N.A.: Algorithms for Physical Design Automation. Kluwer Academic Publishers, Boston (1993)Google Scholar
  9. 9.
    Sarrafzadeh, M., Wang, M., Yang, X.: Modern Placement Techniques. Kluwer Academic Publishers, Boston (2003)Google Scholar
  10. 10.
    Cong, J., Shinnerl, R.: Multilevel Optimization in VLSICAD. Kluwer Academic Publishers, Boston (2003)zbMATHGoogle Scholar
  11. 11.
    Chang, C., Cong, J., Xie, M.: Optimality and Scalability Study of Existing Placement Algorithms. In: ASP-DAC. IEEE Society Computer Press, Los Alamitos (2003)Google Scholar
  12. 12.
    Johann, M., Reis, R.: Net by Net Routing with a New Path Search Algorithm. In: 13th Symposium on Integrated Circuits and Systems Design, Manaus, Proceedings, pp. 144–149. IEEE Computer Society Press, Los Alamitos (2000)CrossRefGoogle Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2003

Authors and Affiliations

  • Ricardo Reis
    • 1
  1. 1.Instituto de InformáticaUniversidade Federal do Rio Grande do SulPorto AlegreBrazil

Personalised recommendations