Abstract
Positive Feedback Adiabatic Logic (PFAL) with minimal dimensioned transistors can save energy compared to static CMOS up to an operating frequency f = 200MHz. In this work the impact of transistor sizing is discussed, and design rules are analytically derived and confirmed by simulations. The increase of the p-channel transistor width can significantly reduce the resistance of the charging path decreasing the energy dissipation of the PFAL inverter by a factor of 2. In more complex gates a further design rule for the sizing of the n-channel transistors is proposed. Simulations of a PFAL 1-bit full adder show that the energy consumption can be reduced by additional 10% and energy savings can be achieved beyond f = 1GHz in a 0.13μm CMOS technology. The results are validated through the use of the design centering tool ‘WiCkeD’ [1].
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Fischer, J., Amirante, E., Randazzo, F., Iannaccone, G., Schmitt-Landsiedel, D. (2003). Reduction of the Energy Consumption in Adiabatic Gates by Optimal Transistor Sizing. In: Chico, J.J., Macii, E. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2003. Lecture Notes in Computer Science, vol 2799. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-39762-5_37
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DOI: https://doi.org/10.1007/978-3-540-39762-5_37
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