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Abstract

Stand-by power reduction for storage circuits, which have to retain data, is obtained through limited locally switched source-body biasing. The stand-by leakage current is reduced by using a source-body bias not exceeding the value that guaranties safe data retention and less leaking non-minimum length transistors. This bias is short-circuited in active mode to improve the speed and the noise margin, especially for low supply voltages; however, this is made for a fraction of the circuit containing the activated part, allowing a trade-off between switching power and leakage. For a SRAM in a 0.18μm process the leakage is reduced more than 25 times without speed or noise margin loss.

Keywords

SRAM Cell Noise Margin Static Leakage Leakage Reduction Static Noise Margin 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2003

Authors and Affiliations

  • S. Cserveny
    • 1
  • J. -M. Masgonty
    • 1
  • C. Piguet
    • 1
  1. 1.CSEM SANeuchâtelCH

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