Stand-by power reduction for storage circuits, which have to retain data, is obtained through limited locally switched source-body biasing. The stand-by leakage current is reduced by using a source-body bias not exceeding the value that guaranties safe data retention and less leaking non-minimum length transistors. This bias is short-circuited in active mode to improve the speed and the noise margin, especially for low supply voltages; however, this is made for a fraction of the circuit containing the activated part, allowing a trade-off between switching power and leakage. For a SRAM in a 0.18μm process the leakage is reduced more than 25 times without speed or noise margin loss.


SRAM Cell Noise Margin Static Leakage Leakage Reduction Static Noise Margin 
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  1. 1.
    Kosonocky, S., Immediato, M., Cottrell, P., Hook, T., Mann, R., Brown, J.: Enhanced Multi-Threshold (MTCMOS) Circuits Using Variable Well Bias. In: Proceedings ISLPED 2001, pp. 165–169 (2001)Google Scholar
  2. 2.
    Narendra, S., Borkar, S., De, V., Antoniadis, D., Chandrakasan, A.: Scaling of Stack Effect and its Application for Leakage Reduction. In: Proceedings ISLPED 2001, pp. 195–200 (2001)Google Scholar
  3. 3.
    Kim, C., Roy, K.: Dynamic Vt SRAM: A Leakage Tolerant Cache Memory for Low Voltage Microprocessors. In: Proceedings ISLPED 2002, pp. 251–254 (2002)Google Scholar
  4. 4.
    Azizi, N., Moshovos, A., Najm, F.: Low-Leakage Asymmetric-Cell SRAM. In: Proceedings ISLPED 2002, pp. 48–51 (2002)Google Scholar
  5. 5.
    Piguet, C., Cserveny, S., Perotto, J.-F., Masgonty, J.-M.: Techniques de circuits et méthods de conception pour réduire la consommation statique dans les technologies profondément submicroniques. In: Proceedings FTFC 2003, pp. 21–29 (2003)Google Scholar
  6. 6.
    Hamzaoglu, F., Stan, M.: Circuit-Level Techniques to Control Gate Leakage for sub- 100nm CMOS. In: Proceedings ISLPED 2002, pp. 60–63 (2002)Google Scholar
  7. 7.
    Masgonty, J.-M., Cserveny, S., Piguet, C.: Low Power SRAM and ROM Memories. In: Proceedings PATMOS 2001, paper 7.4 (2001)Google Scholar
  8. 8.
    Seevinck, E., List, F.J., Lohstroh, J.: Static-Noise Margin Analysis of MOS SRAM Cells. IEEE J. Solid-State Circuits 22, 748–754 (1987)CrossRefGoogle Scholar
  9. 9.
    Bhavnagarwala, A.J., Tang, X., Meindl, J.D.: The Impact of Intrinsic Device Fluctuations on CMOS SRAM Cell Stability. IEEE J. Solid-State Circuits 36, 658–665 (2001)CrossRefGoogle Scholar
  10. 10.
    Enomoto, T., Oka, Y., Shikano, H., Harada, T.: A Self-Controllable-Voltage-Level (SVL) Circuit for Low-Power High-Speed CMOS Circuits. In: Proceedings ESSCIRC 2002, pp. 411–414 (2002)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2003

Authors and Affiliations

  • S. Cserveny
    • 1
  • J. -M. Masgonty
    • 1
  • C. Piguet
    • 1
  1. 1.CSEM SANeuchâtelCH

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