Bridging Clock Domains by Synchronizing the Mice in the Mousetrap

  • Joep Kessels
  • Ad Peeters
  • Suk-Jin Kim
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2799)


We present the design of a first-in first-out buffer that can be used to bridge clock domains in GALS (Globally Asynchronous, Locally Synchronous) systems. Both the input and output side of the buffer have an independently clocked interface. The design of these kind of buffers inherently poses the problems of metastability and synchronization failure. In the proposed design the probability of synchronization failure can be decreased exponentially by increasing the buffer size. Consequently, at system level one can trade off between safety and low latency. The design is based on two well-known ideas: pipeline synchronization and mousetrap buffers. We first combine both ideas and then in several steps improve the design.


Clock Signal VLSI System Asynchronous Circuit Request Signal Maximum Clock Frequency 
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  1. 1.
    van Berkel, K., Huberts, F., Peeters, A.: Stretching quasi delay insensitivity by means of extended isochronic forks. In: Asynchronous Design Methodologies, pp. 99–106. IEEE Computer Society Press, Los Alamitos (1995)CrossRefGoogle Scholar
  2. 2.
    Chapiro, D.M.: Globally-Asynchronous Locally-Synchronous Systems. PhD thesis, Stanford University (October 1984)Google Scholar
  3. 3.
    Chelcea, T., Nowick, S.M.: Robust interfaces for mixed-timing systems with application to latency-insensitive protocols. In: Proc. ACM/IEEE Design Automation Conference (June 2001)Google Scholar
  4. 4.
    Dally, W.J., Poulton, J.W.: Digital Systems Engineering. Cambridge University Press, Cambridge (1998)zbMATHGoogle Scholar
  5. 5.
    Kessels, J., Peeters, A., Wielage, P., Kim, S.-J.: Clock synchronization through handshake signalling. In: Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, April 2002, pp. 59–68 (2002)Google Scholar
  6. 6.
    Martin, A.J.: Programming in VLSI: From communicating processes to delay-insensitive circuits. In: Hoare, C.A.R. (ed.) Developments in Concurrency and Communication. UT Year of Programming Series, pp. 1–64. Addison-Wesley, Reading (1990)Google Scholar
  7. 7.
    Muttersbach, J.: Globally-Asynchronous Locally-Synchronous Architectures for VLSI Systems. PhD thesis, ETH, Zürich (2001)Google Scholar
  8. 8.
    Pečhouček, M.: Anomalous response times of input synchronizers. IEEE Transactions on Computers 25(2), 133–139 (1976)CrossRefGoogle Scholar
  9. 9.
    Seitz, C.L.: System timing. In: Mead, C.A., Conway, L.A. (eds.) Introduction to VLSI Systems,  ch. 7. Addison-Wesley, Reading (1980)Google Scholar
  10. 10.
    Seizovic, J.N.: Pipeline synchronization. In: Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, November 1994, pp. 87–96 (1994)Google Scholar
  11. 11.
    Singh, M., Nowick, S.M.: MOUSETRAP: Ultra-high-speed transitionsignaling asynchronous pipelines. In: Proc. International Conf. Computer Design (ICCD), November 2001, pp. 9–17 (2001)Google Scholar
  12. 12.
    Yun, K.Y., Dooply, A.E.: Pausible clocking-based heterogeneous systems. IEEE Transactions on VLSI Systems 7(4), 482–488 (1999)CrossRefGoogle Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2003

Authors and Affiliations

  • Joep Kessels
    • 1
  • Ad Peeters
    • 1
  • Suk-Jin Kim
    • 2
  1. 1.Philips Research LaboratoriesEindhovenThe Netherlands
  2. 2.Kwang-Ju Institute of Science and TechnologyKwang-juSouth-Korea

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