In this paper an analytical model to estimate crosstalk noise on capacitively and inductively coupled on-chip buses is derived. The analytical nature of the model enables its usage in complex systems where high simulation speed is essential. The model also combines together properties such as inductive coupling, initial conditions, signal rise time, switching time and bit patterns that haven’t been included in a single analytical crosstalk model before. The model is compared to three previous crosstalk noise estimation models. The error of the model remains below four percent when compared to HSPICE. It is also demonstrated that for planar buses the five closest neighboring wires constitute up to 95% of the total induced crosstalk noise.


Rise Time Clock Cycle Switching Time Propagation Delay Couple Line 
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Copyright information

© Springer-Verlag Berlin Heidelberg 2003

Authors and Affiliations

  • Sampo Tuuna
    • 1
  • Jouni Isoaho
    • 1
  1. 1.Laboratory of Electronics and Communication Systems, Department of Information TechnologyUniversity of TurkuTurkuFinland

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