Abstract.
This paper presents the CARE (Compiler Aided Reorder Engine (CARE)) execution and architecture model. CARE is based on a decentralized approach for high-performance microprocessor architecture design – a departure from the mainly centralized control paradigm that dominated the traditional microprocessor architecture evolution. Under CARE, a processor is powered by a large number of fine-grain threads (called strands), each enabled by individual events – such as those due to control dependency or data dependencies with unpredictable and/or long latencies. As a result, the CARE architecture consists of a large grid of small processing cells and their local memories. We outline the CARE architecture design as well as the related issues in strand chaining and synchronization support. Some experimental results are also presented.
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Márquez, A., Gao, G.R. (2003). CARE: Overview of an Adaptive Multithreaded Architecture. In: Veidenbaum, A., Joe, K., Amano, H., Aiso, H. (eds) High Performance Computing. ISHPC 2003. Lecture Notes in Computer Science, vol 2858. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-39707-6_3
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DOI: https://doi.org/10.1007/978-3-540-39707-6_3
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