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High Performance Computing

5th International Symposium, ISHPC 2003, Tokyo-Odaiba, Japan, October 20-22, 2003, Proceedings

  • Conference proceedings
  • © 2003

Overview

Editors:
  1. Alex Veidenbaum

    1. Department of Computer Science, University of California (UCI), Irvine, USA

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  2. Kazuki Joe

    1. Department of Information and Computer Science, Faculty of Science, Nara women’s University, Nara, Japan

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  3. Hideharu Amano

    1. Keio University, Hiyoshi, Kohoku, Yokohama, Kanagawa, Japan

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  4. Hideo Aiso

    1. Tokyo University of Technology, Tokyo, Japan

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Part of the book series: Lecture Notes in Computer Science (LNCS, volume 2858)

Included in the following conference series:

Conference proceedings info: ISHPC 2003.

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Table of contents (50 papers)

  1. Front Matter

    Download chapter PDF

  3. Award Papers

    1. Distinguished Paper Award

      1. Code and Data Transformations for Improving Shared Cache Performance on SMT Processors
        • Dimitrios S. Nikolopoulos
        Pages 54-69

    2. Best Student Paper Award

      1. Improving Memory Latency Aware Fetch Policies for SMT Processors
        • Francisco J. Cazorla, Enrique Fernandez, Alex Ramírez, Mateo Valero
        Pages 70-85

  4. Architecture

    1. Tolerating Branch Predictor Latency on SMT

      • Ayose Falcón, Oliverio J. Santana, Alex Ramírez, Mateo Valero
      Pages 86-98

    2. A Simple Low-Energy Instruction Wakeup Mechanism

      • Marco A. Ramírez, Adrian Cristal, Alexander V. Veidenbaum, Luis Villa, Mateo Valero
      Pages 99-112

    3. Power-Performance Trade-Offs in Wide and Clustered VLIW Cores for Numerical Codes

      • Miquel Pericás, Eduard Ayguadé, Javier Zalamea, Josep Llosa, Mateo Valero
      Pages 113-126

    4. Field Array Compression in Data Caches for Dynamically Allocated Recursive Data Structures

      • Masamichi Takagi, Kei Hiraki
      Pages 127-145

  5. Software

    1. FIBER: A Generalized Framework for Auto-tuning Software

      • Takahiro Katagiri, Kenji Kise, Hiroaki Honda, Toshitsugu Yuba
      Pages 146-159

    2. Evaluating Heuristic Scheduling Algorithms for High Performance Parallel Processing

      • Lars Lundberg, Magnus Broberg, Kamilla Klonowska
      Pages 160-173

    3. Pursuing Laziness for Efficient Implementation of Modern Multithreaded Languages

      • Seiji Umatani, Masahiro Yasugi, Tsuneyasu Komiya, Taiichi Yuasa
      Pages 174-188

    4. SPEC HPG Benchmarks for Large Systems

      • Matthias S. Müller, Kumaran Kalyanasundaram, Greg Gaertner, Wesley Jones, Rudolf Eigenmann, Ron Lieberman et al.
      Pages 189-201

  6. Applications

    1. Distribution-Insensitive Parallel External Sorting on PC Clusters

      • Minsoo Jeon, Dongseung Kim
      Pages 202-213

    2. Distributed Genetic Algorithm for Inference of Biological Scale-Free Network Structure

      • Daisuke Tominaga, Katsutoshi Takahashi, Yutaka Akiyama
      Pages 214-221

    3. Is Cook’s Theorem Correct for DNA-Based Computing?

      • Weng-Long Chang, Minyi Guo, Jesse Wu
      Pages 222-233

    4. LES of Unstable Combustion in a Gas Turbine Combustor

      • Jyunji Shinjo, Yasuhiro Mizobuchi, Satoru Ogawa
      Pages 234-244

  7. ITBL

    1. Grid Computing Supporting System on ITBL Project

      • Kenji Higuchi, Toshiyuki Imamura, Yoshio Suzuki, Futoshi Shimizu, Masahiko Machida, Takayuki Otani et al.
      Pages 245-257
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  1. High Performance Computing

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About this book

The 5th International Symposium on High Performance Computing (ISHPC–V) was held in Odaiba, Tokyo, Japan, October 20–22, 2003. The symposium was thoughtfully planned, organized, and supported by the ISHPC Organizing C- mittee and its collaborating organizations. The ISHPC-V program included two keynote speeches, several invited talks, two panel discussions, and technical sessions covering theoretical and applied research topics in high–performance computing and representing both academia and industry. One of the regular sessions highlighted the research results of the ITBL project (IT–based research laboratory, http://www.itbl.riken.go.jp/). ITBL is a Japanese national project started in 2001 with the objective of re- izing a virtual joint research environment using information technology. ITBL aims to connect 100 supercomputers located in main Japanese scienti?c research laboratories via high–speed networks. A total of 58 technical contributions from 11 countries were submitted to ISHPC-V. Each paper received at least three peer reviews. After a thorough evaluation process, the program committee selected 14 regular (12-page) papers for presentation at the symposium. In addition, several other papers with fav- able reviews were recommended for a poster session presentation. They are also included in the proceedings as short (8-page) papers. Theprogramcommitteegaveadistinguishedpaperawardandabeststudent paper award to two of the regular papers. The distinguished paper award was given for “Code and Data Transformations for Improving Shared Cache P- formance on SMT Processors” by Dimitrios S. Nikolopoulos. The best student paper award was given for “Improving Memory Latency Aware Fetch Policies for SMT Processors” by Francisco J. Cazorla.

Editors and Affiliations

  • Department of Computer Science, University of California (UCI), Irvine, USA

    Alex Veidenbaum

  • Department of Information and Computer Science, Faculty of Science, Nara women’s University, Nara, Japan

    Kazuki Joe

  • Keio University, Hiyoshi, Kohoku, Yokohama, Kanagawa, Japan

    Hideharu Amano

  • Tokyo University of Technology, Tokyo, Japan

    Hideo Aiso

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