Abstract
Modern application scenarios out of the multimedia and mobile communication domains demand more and more performant data processing architectures, which cannot be reached by using actual DSP or microprocessor approaches. This contribution describes a new architecture approach out of the reconfigurable array field which offers a set of new features to increase the flexibility and usability of reconfigurable array architectures by increasing the performance benefit concurrently. The main focus of this publication is the communication topology where the authors will discuss the concepts in detail.
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Thomas, A., Becker, J. (2004). Dynamic Adaptive Runtime Routing Techniques in Multigrain Reconfigurable Hardware Architectures. In: Becker, J., Platzner, M., Vernalde, S. (eds) Field Programmable Logic and Application. FPL 2004. Lecture Notes in Computer Science, vol 3203. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-30117-2_14
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DOI: https://doi.org/10.1007/978-3-540-30117-2_14
Publisher Name: Springer, Berlin, Heidelberg
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