Abstract
The purpose of this chapter is give an overview of the tools we use to translate SAFL(+) to silicon (see Section 10.1) with reference to a realistic example. A DES encryption/decryption circuit is specified in SAFL and implemented on an Altera Apex-II FPGA; area-time performance figures are given (Section 10.2).
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© 2004 Springer-Verlag Berlin Heidelberg
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Sharp, R. (2004). 10. Case Study. In: Higher-Level Hardware Synthesis. Lecture Notes in Computer Science, vol 2963. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-24657-2_10
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DOI: https://doi.org/10.1007/978-3-540-24657-2_10
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-21306-2
Online ISBN: 978-3-540-24657-2
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