Higher-Level Hardware Synthesis

  • Richard Sharp

Part of the Lecture Notes in Computer Science book series (LNCS, volume 2963)

Table of contents

  1. Front Matter
  2. 1. Introduction

    1. Richard Sharp
      Pages 1-18
    2. Richard Sharp
      Pages 19-34
    3. Richard Sharp
      Pages 35-50
    4. Richard Sharp
      Pages 51-64
    5. Richard Sharp
      Pages 65-86
    6. Richard Sharp
      Pages 113-127
    7. Richard Sharp
      Pages 129-139
    8. Richard Sharp
      Pages 141-154
    9. Richard Sharp
      Pages 155-168
    10. Richard Sharp
      Pages 169-170
  3. Appendix

    1. Richard Sharp
      Pages 171-182
  4. Back Matter

About this book

Introduction

In the mid 1960s, when a single chip contained an average of 50 transistors, Gordon Moore observed that integrated circuits were doubling in complexity every year. In an in?uential article published by Electronics Magazine in 1965, Moore predicted that this trend would continue for the next 10 years. Despite being criticized for its “unrealistic optimism,” Moore’s prediction has remained valid for far longer than even he imagined: today, chips built using state-- the-art techniques typically contain several million transistors. The advances in fabrication technology that have supported Moore’s law for four decades have fuelled the computer revolution. However,this exponential increase in transistor density poses new design challenges to engineers and computer scientists alike. New techniques for managing complexity must be developed if circuits are to take full advantage of the vast numbers of transistors available. In this monograph we investigate both (i) the design of high-level languages for hardware description, and (ii) techniques involved in translating these hi- level languages to silicon. We propose SAFL, a ?rst-order functional language designedspeci?callyforbehavioralhardwaredescription,anddescribetheimp- mentation of its associated silicon compiler. We show that the high-level pr- erties of SAFL allow one to exploit program analyses and optimizations that are not employed in existing synthesis systems. Furthermore, since SAFL fully abstracts the low-leveldetails of the implementation technology, we show how it can be compiled to a range of di?erent design styles including fully synchronous design and globally asynchronous locally synchronous (GALS) circuits.

Keywords

Hardware SAFL VHDL VLSI specifications Verilog compiler complexity functional languages hardware description languages hardware design hardware synthesis hardware/software codesign systems design systems optimization systems specification

Authors and affiliations

  • Richard Sharp
    • 1
  1. 1.Intel ResearchCambridgeUK

Bibliographic information

  • DOI https://doi.org/10.1007/b95732
  • Copyright Information Springer-Verlag Berlin Heidelberg 2004
  • Publisher Name Springer, Berlin, Heidelberg
  • eBook Packages Springer Book Archive
  • Print ISBN 978-3-540-21306-2
  • Online ISBN 978-3-540-24657-2
  • Series Print ISSN 0302-9743
  • Series Online ISSN 1611-3349
  • About this book
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