Abstract
In DSAL, vias that are physically close are clustered and patterned together through a guide pattern (GP) [1, 2]. A large and complex GP is not allowed to form because it is likely to cause a pattern failure on a wafer. This chapter addresses redundant via insertion problem for DSAL. The goal is to maximally insert redundant vias while vias (both original and redundant) are clustered to form only desirable GPs. The problem can be formulated as finding maximum independent set (MIS) of a conflict graph. Experiments demonstrate that 13% more redundant vias are inserted compared to simple-minded approach, in which a basic insertion with no consideration of DSAL is followed by removal of redundant vias that cause undesirable GPs. DSA defect probability of via cluster is addressed in order to quantitatively define which GPs are allowed during the redundant via insertion process.
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Notes
- 1.
Once redundant via is inserted, metal wires of the same net are locally modified so that the redundant via can be connected. For example, if \(R_1\) is selected, metal 1 and 2 are extended so that both \(O_1\) and \(R_1\) are connected.
- 2.
Remember that defect probability calculation is somewhat conservative, so clusters with very low defect probability may not actually cause any defects. Precise decision of which probability should be accepted is up to manufacturing details.
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Shim, S., Shin, Y. (2018). Redundant Via Insertion for DSAL. In: Physical Design and Mask Synthesis for Directed Self-Assembly Lithography. NanoScience and Technology. Springer, Cham. https://doi.org/10.1007/978-3-319-76294-4_5
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DOI: https://doi.org/10.1007/978-3-319-76294-4_5
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