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Performance-Limiting Traps in GaN-Based HEMTs: From Native Defects to Common Impurities

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Power GaN Devices

Part of the book series: Power Electronics and Power Systems ((PEPS))

Abstract

This chapter describes the properties of the performance-limiting defects in GaN-based transistors. The first part of the chapter summarizes the properties of the most common defects in GaN, by describing a database of defects that has been prepared by our group based on a collection of more than 80 papers on the topic. The second part of the chapter describes the results of our most recent experiments on the impact of common native defects (vacancies, surface states, etc.) and impurities (such as Fe and C) on the dynamic performance of GaN HEMTs. Information on the correlation between epitaxial structure, process quality, and dynamic performance is given in the text.

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  1. Department of Information Engineering, University of Padova, Padua, Italy

    Isabella Rossetto, Davide Bisi, Carlo de Santi, Antonio Stocco, Gaudenzio Meneghesso, Enrico Zanoni & Matteo Meneghini

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    Matteo Meneghini

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    Gaudenzio Meneghesso

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    Enrico Zanoni

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Rossetto, I. et al. (2017). Performance-Limiting Traps in GaN-Based HEMTs: From Native Defects to Common Impurities. In: Meneghini, M., Meneghesso, G., Zanoni, E. (eds) Power GaN Devices. Power Electronics and Power Systems. Springer, Cham. https://doi.org/10.1007/978-3-319-43199-4_9

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