Abstract
This chapter gives an overview of the proposed analog integrated circuit (IC) design automation environment, AIDA, which implements a design flow from a circuit-level (spice netlist) specification to a physical layout (GDSII stream) description. The emphasis is on the automatic analog IC sizing and optimization tool, AIDA-C, but a brief overview of AIDA-L, the layout generation tool, is also provided, as it is an indispensable module to enable layout-aware sizing and optimization. In the first section, the AIDA environment for analog IC design automation is presented and in Sect. 3.2 the sizing capabilities of AIDA-C circuit optimizer are sketched. Finally, in Sect. 3.3, additional detail about the tool’s implementation, inputs, outputs and proposed design flow is provided.
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Lourenço, N., Martins, R., Horta, N. (2017). AIDA-C Architecture. In: Automatic Analog IC Sizing and Optimization Constrained with PVT Corners and Layout Effects. Springer, Cham. https://doi.org/10.1007/978-3-319-42037-0_3
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DOI: https://doi.org/10.1007/978-3-319-42037-0_3
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