Skip to main content
SpringerLink
Log in

Layout Decomposition for Other Patterning Techniques

  • Chapter
Design for Manufacturability with Advanced Lithography

  • 1144 Accesses

Abstract

So far we have discussed the conventional process of TPL, called LELELE, which follows the same principle as litho-etch-litho-etch (LELE) type double patterning lithography (DPL). Here each “L” and “E” represents one lithography process and one etch process, respectively. Although LELELE has been widely studied by industry and academia, it still has two major issues. First, even with stitch insertion, there are some native conflicts in LELELE, like four-clique conflict [1]. For example, Fig. 3.1 illustrates a four-clique conflict among features a, b, c, and d. No matter how we assign the colors, there will be at least one conflict. Since this four-clique structure is common in advanced standard cell design, LELELE type TPL suffers from the native conflict problem. Second, compared to LELE type double patterning, there are more serious overlapping problems in LELELE [2].

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Log in via an institution
Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 39.99
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 54.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD 54.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Notes

  1. 1.

    In QPLD problem, the vertices with degree less than 4 would be detected and removed temporally.

References

  1. Yu, B., Yuan, K., Zhang, B., Ding, D., Pan, D.Z.: Layout decomposition for triple patterning lithography. In: IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 1–8 (2011)

    Google Scholar 

  2. Ausschnitt, C., Dasari, P.: Multi-patterning overlay control. In: Proceedings of SPIE, vol. 6924 (2008)

    Google Scholar 

  3. Lin, B.J.: Lithography till the end of Moore’s law. In: ACM International Symposium on Physical Design (ISPD), pp. 1–2 (2012)

    Google Scholar 

  4. Banerjee, S., Li, Z., Nassif, S.R.: ICCAD-2013 CAD contest in mask optimization and benchmark suite. In: IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 271–274 (2013)

    Google Scholar 

  5. Mack, C.: Fundamental Principles of Optical Lithography: The Science of Microfabrication. Wiley, New York (2008)

    Google Scholar 

  6. Cork, C., Madre, J.-C., Barnes, L.: Comparison of triple-patterning decomposition algorithms using aperiodic tiling patterns. In: Proceedings of SPIE, vol. 7028 (2008)

    Google Scholar 

  7. Fang, S.-Y., Chen, W.-Y., Chang, Y.-W.: A novel layout decomposition algorithm for triple patterning lithography. In: ACM/IEEE Design Automation Conference (DAC), pp. 1185–1190 (2012)

    Google Scholar 

  8. Tian, H., Zhang, H., Ma, Q., Xiao, Z., Wong, M.D.F.: A polynomial time triple patterning algorithm for cell based row-structure layout. In: IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 57–64 (2012)

    Google Scholar 

  9. Kuang, J., Young, E.F.: An efficient layout decomposition approach for triple patterning lithography. In: ACM/IEEE Design Automation Conference (DAC), pp. 69:1–69:6 (2013)

    Google Scholar 

  10. Yu, B., Lin, Y.-H., Luk-Pat, G., Ding, D., Lucas, K., Pan, D.Z.: A high-performance triple patterning layout decomposer with balanced density. In: IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 163–169 (2013)

    Google Scholar 

  11. Zhang, Y., Luk, W.-S., Zhou, H., Yan, C., Zeng, X.: Layout decomposition with pairwise coloring for multiple patterning lithography. In: IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 170–177 (2013)

    Google Scholar 

  12. Yu, B., Pan, D.Z.: Layout decomposition for quadruple patterning lithography and beyond. In: ACM/IEEE Design Automation Conference (DAC), pp. 53:1–53:6 (2014)

    Google Scholar 

  13. Ma, Q., Zhang, H., Wong, M.D.F.: Triple patterning aware routing and its comparison with double patterning aware routing in 14nm technology. In: ACM/IEEE Design Automation Conference (DAC), pp. 591–596 (2012)

    Google Scholar 

  14. Lin, Y.-H., Yu, B., Pan, D.Z., Li, Y.-L.: TRIAD: a triple patterning lithography aware detailed router. In: IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 123–129 (2012)

    Google Scholar 

  15. Tian, H., Du, Y., Zhang, H., Xiao, Z., Wong, M.D.F.: Constrained pattern assignment for standard cell based triple patterning lithography. In: IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 178–185 (2013)

    Google Scholar 

  16. Yu, B., Xu, X., Gao, J.-R., Pan, D.Z.: Methodology for standard cell compliance and detailed placement for triple patterning lithography. In: IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 349–356 (2013)

    Google Scholar 

  17. Kahng, A.B., Park, C.-H., Xu, X., Yao, H.: Layout decomposition for double patterning lithography. In: IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 465–472 (2008)

    Google Scholar 

  18. Sun, J., Lu, Y., Zhou, H., Zeng, X.: Post-routing layer assignment for double patterning. In: IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC), pp. 793–798 (2011)

    Google Scholar 

  19. Cormen, T.T., Leiserson, C.E., Rivest, R.L.: Introduction to Algorithms. MIT Press, Cambridge (1990)

    MATH  Google Scholar 

  20. Yu, B., Gao, J.-R., Pan, D.Z.: Triple patterning lithography (TPL) layout decomposition using end-cutting. In: Proceedings of SPIE, vol. 8684 (2013)

    Google Scholar 

  21. Xu, Y., Chu, C.: A matching based decomposer for double patterning lithography. In: ACM International Symposium on Physical Design (ISPD), pp. 121–126 (2010)

    Google Scholar 

  22. Yuan, K., Yang, J.-S., Pan, D.Z.: Double patterning layout decomposition for simultaneous conflict and stitch minimization. In: ACM International Symposium on Physical Design (ISPD), pp. 107–114 (2009)

    Google Scholar 

  23. Yang, J.-S., Lu, K., Cho, M., Yuan, K., Pan, D.Z.: A new graph-theoretic, multi-objective layout decomposition framework for double patterning lithography. In: IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC), pp. 637–644 (2010)

    Google Scholar 

  24. Gurobi Optimization Inc.: Gurobi optimizer reference manual. http://www.gurobi.com (2014)

  25. Karger, D., Motwani, R., Sudan, M.: Approximate graph coloring by semidefinite programming. J. ACM 45, 246–265 (1998)

    Article  MATH  MathSciNet  Google Scholar 

  26. Appel, K., Haken, W.: Every planar map is four colorable. Part I: discharging. Ill. J. Math. 21(3), 429–490 (1977)

    MATH  MathSciNet  Google Scholar 

  27. Kuratowski, C.: Sur le probleme des courbes gauches en topologie. Fundam. Math. 15(1), 271–283 (1930)

    MATH  MathSciNet  Google Scholar 

  28. Robertson, N., Sanders, D.P., Seymour, P., Thomas, R.: Efficiently four-coloring planar graphs. In: ACM Symposium on Theory of computing (STOC), pp. 571–575 (1996)

    Google Scholar 

  29. Tang, X., Cho, M.: Optimal layout decomposition for double patterning technology. In: IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 9–13 (2011)

    Google Scholar 

  30. Gomory, R.E., Hu, T.C.: Multi-terminal network flows. J. Soc. Ind. Appl. Math. 9(4), 551–570 (1961)

    Article  MATH  MathSciNet  Google Scholar 

  31. Gusfield, D.: Very simple methods for all pairs network flow analysis. SIAM J. Comput. 19(1), 143–155 (1990)

    Article  MATH  MathSciNet  Google Scholar 

  32. Dinic, E.A.: Algorithm for solution of a problem of maximum flow in networks with power estimation. Sov. Math. Dokl 11(5), 1277–1280 (1970)

    Google Scholar 

  33. Borchers, B.: CSDP, a C library for semidefinite programming. Optim. Methods Softw. 11, 613–623 (1999)

    Article  MathSciNet  Google Scholar 

Download references

Author information

Authors and Affiliations

  1. ECE Department, The University of Texas, Austin, TX, USA

    Bei Yu & David Z. Pan

Authors
  1. Bei Yu
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. David Z. Pan
    View author publications

    You can also search for this author in PubMed Google Scholar

Rights and permissions

Reprints and permissions

Copyright information

© 2016 Springer International Publishing Switzerland

About this chapter

Cite this chapter

Yu, B., Pan, D.Z. (2016). Layout Decomposition for Other Patterning Techniques. In: Design for Manufacturability with Advanced Lithography. Springer, Cham. https://doi.org/10.1007/978-3-319-20385-0_3

Download citation

  • DOI: https://doi.org/10.1007/978-3-319-20385-0_3

  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-319-20384-3

  • Online ISBN: 978-3-319-20385-0

  • eBook Packages: EngineeringEngineering (R0)

Publish with us

Policies and ethics

Search

Navigation