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Recent Advances and Trends in High-Performance Embedded Data Converters

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High-Performance AD and DA Converters, IC Design in Scaled Technologies, and Time-Domain Signal Processing

Abstract

This chapter discusses the architectures of Nyquist rate Analog-to-Digital Converters (ADCs), that are embedded in systems-on-chip (SoCs) implementing some of the most widespread mobile communication, wireless and wireline connectivity standards. The typical requirements for these ADCs are presented, and the main conversion architectures are described in terms of the fundamental operations realized inside them. This constitutes a unified treatment that relates all architectures, thus providing a deeper understanding of their fundamental limitations and trade-offs. We then discuss some of the solutions recently published in the literature to improve ADC energy efficiency. Finally we disclose implementation details from two 12 bit digitally calibrated, high-speed ADCs, using the pipeline and SAR architectures.

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Notes

  1. 1.

    Nyquist rate architectures are those theoretically capable of digitizing signals with a bandwidth up to half of the sampling rate. Sigma-Delta, another major class of converters, handles narrow band input signals and employs oversampling and noise shaping to increase resolution.

  2. 2.

    Orthogonal Frequency-Division Multiplexing (OFDM) is used in a variety of systems (802.11, WiMAX, LTE, G.hn, etc.), to cope with severe non-idealities of transmission mediums, such as high frequency attenuation in copper wires or frequency dependent fading due to multipath propagation [3, 12]. In OFDM each channel is composed of a number of closely spaced orthogonal sub-carriers, and the exact ADC sampling frequency is typically a multiple of the sub-carrier separation.

  3. 3.

    Note that actual 1 bit ADC implementations may not include a dedicated S/H circuit. However the sampling operation happens anyway, because when the comparator is triggered it decides based on the input signal value at that time. (There are publications, mainly in the 80’s, where no dedicated S/H exists in front of flash ADCs [40, 41].) So the presence of the S/H in Fig. 5 is meant to imply that this operation is performed, and not that there is necessarily a dedicated circuit implementing it. Similar considerations apply to the discussion in the remainder of this section. For example [42] does not use dedicated comparator circuits, but the comparison operations still take place.

  4. 4.

    We are referring to those affecting the ADC static transfer function. There is also noise, limited bandwidth, memory effects, etc., but as previously mentioned those are beyond the scope of this text.

  5. 5.

    The residue is the error corresponding to the difference between the input signal and the result from the quantization performed so far, which is provided by the DAC. Figure 6a shows the residue being applied to a single-bit quantizer (comparator), but it may be applied to multi-bit quantizers (see Sect. 3.4.).

  6. 6.

    Alternatively, an output dependent offset could be considered, which would add to the offsets of the subtractors/comparators.

  7. 7.

    These have the downside of introducing attenuation, which increases the input referred values of the comparator’s offsets [32].

  8. 8.

    This is used in the quantizer of the last stage, on the pipeline ADC described in that reference.

  9. 9.

    This is the most frequent case on pipeline ADC. However, as discussed at the end of this sub-section there are, for example, (two-stage) implementations with low gain residue amplification, where the stages receive different reference voltages.

  10. 10.

    There are pipeline ADC implementations employing a small number of stages, each with a higher resolution. In those cases the quantizers are more complex, must comply with tighter specifications, and consume more power. References [33, 63] address these limitations by using SAR ADC quantizers instead of the traditional flash ADCs, thereby improving power efficiency. Furthermore there is only one comparator whose offset must be made low enough.

    Reference [59] implements the 7 bit quantizer in its last stage as a two-step subranging ADC composed of a coarse flash ADC and a fine SAR ADC. The 4.5bit quantizers (the meaning of this will be explained shortly) used on the other stages are also two-step subranging converters, but with coarse and fine flash ADCs. There is redundancy inside all these two-step quantizers to relax the specifications of their coarse ADCs. Naturally, there is also redundancy between the pipelined stages, as just explained.

  11. 11.

    The “1.5 bit stage” designation may seem odd but this simply means its flash ADC has 3 output codes, which is halfway between the number of codes encountered on a “1 bit” and on a “2 bit” ADC.

  12. 12.

    Some authors [64] call this a 2.8bit stage, because the quantizer provides 7 output codes, and log2(7) ≈ 2.8.

  13. 13.

    Naturally the non-idealities of the MDAC can be traced to those of the basic operations it implements.

  14. 14.

    The quantizer is not affected by this offset error. From the perspective of the MDAC it is as if the code transition voltages of the quantizer are shifted, but this is not a problem due to redundancy.

  15. 15.

    The quantizer is not affected by this gain error. From the perspective of the MDAC it is as if the code transition voltages of the quantizer are shifted, but this is not a problem due to redundancy.

  16. 16.

    Figure 20 illustrates how the 1.5 bit stage is derived from a 2 bit stage. The 1.5 bit stage is addressed by considering N 1 = 2 in the model shown in Fig. 23. Likewise, for a 2.5 bit stage one should consider N 1 = 3 and so on.

  17. 17.

    With the supply voltage reduction at more advanced technology nodes, one must bias the MOS transistors with lower overdrive voltages, v OVD  = v GS  − V th . In the past it was necessary to bias transistors far into strong inversion (v OVD  > 0.2 V), to achieve the necessary operating speed. However transistors in modern technologies present large transit frequencies even for low or negative v OVD [30], which enables designers to use reduced overdrive voltages.

  18. 18.

    Since MOS gate capacitance is inversely proportional to oxide thickness, it increases for more advanced technologies. If transistor sizes cannot be significantly reduced, the capacitances will become larger, which may eventually increase the power consumption.

  19. 19.

    The S/H must be linear, but it can frequently be implemented without active elements.

  20. 20.

    And also in folding and interpolation ADCs, which were not discussed in this manuscript because currently they are not frequently used.

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  1. Synopsys, Lagoas Park – Edifício 4, 2 Piso, 2740-267, Porto-Salvo, Portugal

    Pedro Figueiredo

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  1. Pedro Figueiredo
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  1. Department of Electrical Engineering, Eindhoven University of Technology, Eindhoven, The Netherlands

    Pieter Harpe

  2. Department of Physics, University of Milan-Bicocca, Milan, Italy

    Andrea Baschirotto

  3. Delft University of Technology, Delft, The Netherlands

    Kofi A. A. Makinwa

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Figueiredo, P. (2015). Recent Advances and Trends in High-Performance Embedded Data Converters. In: Harpe, P., Baschirotto, A., Makinwa, K. (eds) High-Performance AD and DA Converters, IC Design in Scaled Technologies, and Time-Domain Signal Processing. Springer, Cham. https://doi.org/10.1007/978-3-319-07938-7_5

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