Abstract
In this chapter, we review the operating principles of the main topologies of ADPLLs (PFD-plus-TDC-based, TDC-based and accumulator-based ADPLLs) in terms of the integer and fractional parts of the phase difference. We also mention the flip-flop-based ADPLL which can be considered as a particular case of a TDC-based ADPLL. We show models that describe the phase-to-digital conversion in each ADPLL architecture when the integer part of the phase difference is equal to or different from zero. We show that a flip-flop based ADPLL can be viewed as the ADPLL architecture with the simplest phase-to-digital conversion. We also discuss possible strategies to clock the digital filter in the various ADPLL architectures. We show how to modify the ADPLL architectures to synthesize a fractional ratio between the frequencies of the reference oscillator and the DCO. Finally, we compare the ADPLL architectures in terms of phase-to-digital conversion, TDC dynamic range, and metastability.
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Notes
- 1.
The durations of the periods of \(T_{\textit{Div}}\) can be estimated from the input of the DCO.
- 2.
We assume a generic digital filter with one pole in the origin in order to have a type-II PLL. Moreover, additional zeros and poles have to be in the left hand plane to guarantee a stable loop.
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Brandonisio, F., Kennedy, M.P. (2014). Phase Digitization in All-Digital PLLs. In: Noise-Shaping All-Digital Phase-Locked Loops. Analog Circuits and Signal Processing. Springer, Cham. https://doi.org/10.1007/978-3-319-03659-5_2
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