An Introduction to High-Speed DRAM

Abstract

Synchronous dynamic random access memory (SDRAM) has been widely used in various systems. From DDR1 to GDDR5, the operating speed has been rapidly increased to keep pace with the performance of application system. Up to now, 7 Gb/s/pin GDDR5 is the fastest SDRAM adopted in graphics cards (R. Rho et al., IEEE J. Solid-State Circuits, vol. 45, no. 1, pp. 120–133, 2010; T.-Y. Oh et al., IEEE J. Solid-State Circuits, vol. 46, no. 1, pp. 120–133, 2011; D. Shin et al., IEEE Symp. on Very Large Scale Integr. Circuits Dig. Tech. Papers, pp. 138–139, 2009). However, the DRAM’s core speed cannot be increased due to technical limits. Other approaches are required to solve the limited core speed. In addition, scaling limits and increased lithography costs make it hard for DRAM vendors to increase the density of DRAM. Wide I/O DRAM is one alternative type of memory, as is TSV-based stacked memory. In this chapter, we introduce the fundamentals of high-speed DRAM operation. We do not cover the basic knowledge of complementary metal-oxide semiconductor (CMOS) circuits including design, layout, and simulation.