Implementation of the Low Power Transceiver

Abstract

This chapter describes the implementation of the proposed transceiver at the circuit level. Being a key building block in any narrow-band receiver, the first section of the chapter begins with the design of the frequency synthesizer, in particular, the evaluation of the different topologies for low-power quadrature generation. Then, the selected topology, namely a quadrature voltage controlled oscillator (QVCO), is refined for improved accuracy and extended to implement direct modulation. The second section describes the design of the RF front-end, where the main focus is to maximize the internal RF impedance using a transformer. In the third section, the base-band part of the receiver is detailed, whose key element is a demodulator using a 4-bit Ph-ADC. Finally, the performance of the transceiver as a whole is evaluated, also in conjunction with a commercially available BLE transceiver. In TX-mode a power consumption of 5.9 mW is measured for delivering an output power of 1.6 dBm to the antenna, which corresponds to a total efficiency of 24.5 %. In RX-mode, the transceiver consumes only 1.1 mW and achieves a sensitivity of −81.4 dBm using a passive RF front-end topology without LNA.