Abstract
Spin-transfer torque random access memory (STT-RAM) has recently gained increased attention from circuit design and architecture societies. Although STT-RAM offers a good combination of small cell size, nanosecond access time and non-volatility for embedded memory applications, the reliability of STT-RAM is severely impacted by device variations and environmental disturbances. In this work, we develop a compact switching model for magnetic tunneling junction (MTJ), which is the data storage device in STT-RAM cells. By leveraging the capability to simulate the impact of thermal and process variations on MTJ switching, our model is able to analyze the diverse mechanisms of STT-RAM write operation failures. Besides the impacts of thermal and process variation, the soft error induced by radiation striking on the access transistor is another important threat to the MTJ reliability. It can also be analyzed by using our model. The incurred computation cost of our model is much less than the conventional macro-magnetic model, and hence, enabling its applications in comprehensive STT-RAM reliability analysis and design optimizations.
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Acknowledgment
This work is supported by NSF award: CNS-1116171 and CCF-1217947.
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Wang, P., Eken, E., Zhang, W., Joshi, R., Kanj, R., Chen, Y. (2015). A Thermal and Process Variation Aware MTJ Switching Model and Its Applications in Soft Error Analysis. In: Topaloglu, R. (eds) More than Moore Technologies for Next Generation Computer Design. Springer, New York, NY. https://doi.org/10.1007/978-1-4939-2163-8_5
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DOI: https://doi.org/10.1007/978-1-4939-2163-8_5
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