Abstract
The number of MOSFETs in a single CMOS microprocessor chip exceeded one billion in the year 2010 and this trend has continued. Tracking the behavior of individual MOSFETs on CMOS chips in electrical testing is a daunting task. This task is simplified by following the hierarchical nature of chip architecture. Repetitive patterns in data transactions and in writing and reading data in memory arrays are implemented with a small subset of building blocks. At the next level down in the hierarchy, logic gates, storage elements, and memory cells can be independently characterized and their behaviors related to the properties of their constituent MOSFETs, interconnects, and parasitic resistances and capacitances. Circuit simulation examples to directly extract cycle time and noise margins of an SRAM cell are included.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
References
Henessy JL, Patterson DA (2011) The basics of logic design. In: Computer organization and design, Appendix C. Morgan Kaufmann Publishers, San Francisco
Rabaey JM, Chandrakasan A, Nikolic B (2003) Digital integrated circuits, 2nd edn. Prentice Hall, Upper Saddle River
Weste NH, Harris D (2010) CMOS VLSI design: a circuit and systems perspective, 4th edn. Addison-Wesley, Boston
Haraszti TP (2000) CMOS memory circuits. Kluwer Academic Publishers, Boston
Xanthopoulos T (ed) (2009) Clocking in modern VLSI systems. Springer, Berlin
Warnock J, Sigal L, Wendel D, Muller KP, Friedrich J, et al. (2010) POWER7 local clocking and clocked storage elements. In: 2010 I.E. international solid-state circuits conference, pp 178–179
Bhushan M, Ketchen MB, Das KK (2008) CMOS latch metastability characterization at the 65-nm-technology node. In: Proceedings of the 2008 I.E. international conference on microelectronic test structures, pp 147–151
Seevinck E, List FJ, Lohstroh J (1987) Static-noise margin analysis of MOS SRAM cells. IEEE J Solid-State Circuits 22:748–754
Author information
Authors and Affiliations
Rights and permissions
Copyright information
© 2015 Springer Science+Business Media New York
About this chapter
Cite this chapter
Bhushan, M., Ketchen, M.B. (2015). CMOS Storage Elements and Synchronous Logic. In: CMOS Test and Evaluation. Springer, New York, NY. https://doi.org/10.1007/978-1-4939-1349-7_3
Download citation
DOI: https://doi.org/10.1007/978-1-4939-1349-7_3
Published:
Publisher Name: Springer, New York, NY
Print ISBN: 978-1-4939-1348-0
Online ISBN: 978-1-4939-1349-7
eBook Packages: EngineeringEngineering (R0)