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Nonvolatile Circuit Design

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Design Exploration of Emerging Nano-scale Non-volatile Memory

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Abstract

Memory design is commonly composed of two parts: the data arrays and the peripheral circuits. The data array is essentially a two-dimensional expansion of memory cells repetitively, which determines the way to retrieve data from particular cells in the array with limited I/O interface. The peripheral circuits mainly include many levels of decoders as well as readout sense amplifiers. Due to the use of nonelectrical states of emerging nonvolatile memory devices, new cells structures as well as agreeing readout circuits are needed for their unique read and write operations with performance evaluation. In this chapter, three different memory cell designs, crossbar structure for ReRAM, 1T1R structure for STT-RAM, and tape-like structure for domain-wall nanowire, are discussed with the agreeing readout circuits illustrated. Their performance models are presented as well if they are different from traditional designs.

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Authors and Affiliations

  1. School of EEE, Nanyang Technological University, Singapore, Singapore

    Hao Yu & Yuhao Wang

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  1. Hao Yu
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  2. Yuhao Wang
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Yu, H., Wang, Y. (2014). Nonvolatile Circuit Design. In: Design Exploration of Emerging Nano-scale Non-volatile Memory. Springer, New York, NY. https://doi.org/10.1007/978-1-4939-0551-5_4

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  • DOI: https://doi.org/10.1007/978-1-4939-0551-5_4

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  • Print ISBN: 978-1-4939-0550-8

  • Online ISBN: 978-1-4939-0551-5

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