Abstract
IC manufacturers have traditionally met customers’ demands for ever increasing chip processing capability by decreasing feature size. The alternative -- significantly increasing the chip area -- has thus far not been economically competitive, owing primarily to the low yield of larger circuit areas [1].
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© 1989 Plenum Press, New York
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Cosentino, R.J., Johnson, B.L., Vaccaro, J.J. (1989). Combining Architecture and Algorithm for Yield Enhancement and Fault Tolerance. In: Koren, I. (eds) Defect and Fault Tolerance in VLSI Systems. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-6799-8_7
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DOI: https://doi.org/10.1007/978-1-4615-6799-8_7
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