Abstract
Fault tolerance techniques have been adopted historically in discrete-component computing systems as a consequence of particular applications which demanded high reliability and availability.
This work was partially sponsored by NATO and AT&T.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Leighton, T., and C.E. Leiseron, “Wafer-Scale Integration of Systolic Arrays,” IEEE Trans. on Computers, Vol. C34, No. 5, pp. 448–461, 1985.
Rosenberg, A.L., “The Diogenes Approach to Testable Fault Tolerant VLSI Processor Arrays,” IEEE Trans. on Computers, Vol. C-32, No. 10, pp. 902–910, 1983.
Negrini, R., M.G. Sami and R. Stefanelli, “Fault Tolerance Technique for Array Structures used in Supercomputing,” IEEE Computer Magazine, Vol. 19, No. 2, pp. 78–87, 1986.
Hedlund, K. and L. Snyder, “Systolic Architecture–A Wafer-Scale Approach,” Proc. ICCD, pp. 604–610, 1984.
Greene, J.W. and A. El Gamal, “Configuration of VLSI Arrays in the Presence of Defects,” J. ACM, Vol. 31, No. 4, pp. 694–717, 1984.
Snyder, L., “Introduction to the Configurable Highly Parallel Computer,” IEEE Computer Magazine, Vol. 15, No. 1, pp. 47–56, 1982.
Fortes, J.A.B. and C.S. Raghavendra, “Gracefully Degradable Processor Arrays,” IEEE Trans. on Computer, Vol. C-34, No. 11, pp. 1033–1044, 1985.
Lombardi, F., M.G., Sami and R. Stefanelli, “Reconfiguration of VLSI Arrays: An Index Mapping Approach,” Proc. IEEE Compeuro, pp. 60–65, 1987.
Aubusson, R.C. and I. Catt, “Wafer-Scale Integration: A Fault Tolerant Procedure,” IEEE J. Solid-State Circuits, Vol. SC3, No. 3, pp., June 1978.
Lombardi, F., R. Negrini, M.G. Sami and R. Stefanelli, “Reconfiguration of VLSI Arrays: A Covering Approach,” Proc. FTCS17, pp. 251–256, 1987.
Evans, R.A., “A Self-organizing Fault-Tolerant 2-D Array,” Proc. VLSI, Tokyo, Japan, 1985.
Chandramouli, R. and M. Sucar, “Defect Analysis and Fault Modeling in MOS Technology,” Proc. Int. Test Conf., pp. 313–321, 1985.
Stapper, C.H., “On Yield, Fault Distributions, and Clustering of Particles,” J. Res. Develop., Vol. 30, No. 3, 1986.
Lombardi, F and D. Sciuto, “Reconfiguration in WSI Arrays Using Minimum Spanning Trees,” Proc. IEEE Compeuro, pp. 547–550, 1987.
Mangir, T.E., “Sources of Failure and Yield Improvement for VLSI and Restructurable Interconnect for R-VLSI and WSI: Part II”, Proc. IEEE, No. 12, pp. 1687–1694, 1984.
Howell, M.C. and V.K. Agarwal, “Yield and Reliability Enhancement of Large Area Binary Tree Architectures,” Proc. FTCS 17, pp. 290–295, 1987.
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 1989 Plenum Press, New York
About this chapter
Cite this chapter
Jervis, L., Lombardi, F., Sciuto, D. (1989). Orthogonal Mapping: A Reconfiguration Strategy for Fault Tolerant VLSI/WSI 2-D Arrays. In: Koren, I. (eds) Defect and Fault Tolerance in VLSI Systems. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-6799-8_27
Download citation
DOI: https://doi.org/10.1007/978-1-4615-6799-8_27
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4615-6801-8
Online ISBN: 978-1-4615-6799-8
eBook Packages: Springer Book Archive