Abstract
Defect identification, monitoring and yield play an important role in VLSI circuit manufacturing.
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References
Stapper, C.H., “Yield Statistics for Large Area ICs”, ISSCC Digest of Technical Papers, pp. 168–169, February 1986.
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© 1989 Plenum Press, New York
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Magdo, S. (1989). Yield Model for Yield Projection from Test Site. In: Koren, I. (eds) Defect and Fault Tolerance in VLSI Systems. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-6799-8_12
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DOI: https://doi.org/10.1007/978-1-4615-6799-8_12
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4615-6801-8
Online ISBN: 978-1-4615-6799-8
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