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Exploiting Parallelism in Leaf-Macro Access

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Testability Concepts for Digital ICs

Part of the book series: Frontiers in Electronic Testing ((FRET,volume 3))

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Abstract

The Macro Test concept provides a route from IC design to a set of leaf-macro test specifications. The major steps to follow are test plan generation, test pattern generation, and test pattern insertion; see Chapter 3. The test specifications contain the information of where to apply and observe given data at a specified time frame. A complete device test specification is produced by merging all leaf-macro test specifications. This process is called test assembly; see Chapter 3.

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© 1995 Springer Science+Business Media Dordrecht

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Beenker, F.P.M., Bennetts, R.G., Thijssen, A.P. (1995). Exploiting Parallelism in Leaf-Macro Access. In: Testability Concepts for Digital ICs. Frontiers in Electronic Testing, vol 3. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-2365-9_7

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  • DOI: https://doi.org/10.1007/978-1-4615-2365-9_7

  • Publisher Name: Springer, Boston, MA

  • Print ISBN: 978-1-4613-6004-9

  • Online ISBN: 978-1-4615-2365-9

  • eBook Packages: Springer Book Archive

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