Abstract
This chapter presents experimental investigation and statistical modeling of charge trapping in the context of random telegraph noise (RTN) and bias temperature instability (BTI). The goal is to develop circuit (electrical) level models to support circuit designers. The developed modeling approach is based on discrete device physics quantities, which are shown to cause statistical variability in the electrical behavior of MOSFETs. Besides evaluating the average behavior, the modeling approach here proposed allows the derivation of statistically relevant parameters. It allows the derivation of an analytical formulation for the both noise (RTN) and aging (BTI) behavior. Monte Carlo simulations are also discussed and presented. Good agreement between experimental data, Monte Carlo simulations, and model is found.
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References
G Wirth et al. “Modeling of Statistical Low-Frequency Noise of Deep-Submicron MOSFETs”, IEEE Trans. Electron Dev., 52, p. 1576 (2005).
G Wirth, R da Silva and R Brederlow. “Statistical Model for the Circuit Bandwidth Dependence of Low-Frequency Noise in Deep-Submicrometer MOSFETs”, IEEE Trans. Electron Dev., 54, p. 340–345 (2007).
G Wirth et al. “Statistical model for MOSFET low-frequency noise under cyclo-stationary conditions” Int Electron Dev Meeting - IEDM 2009, p. 30.5.1 (2009).
G Wirth and R da Silva, “Low-Frequency Noise Spectrum of Cyclo-Stationary Random Telegraph Signals”, Electrical Eng., 90, p. 435 (2008).
R da Silva, G Wirth and L Brusamarello. “An appropriate model for the noise power spectrum produced by traps at the Si SiO interface: a study of the influence of a time-dependent Fermi level. Journal of Statistical Mechanics” J. of Statistical Mechanics. Theory and Experiment, 2008, p. P10015 (2008).
R Brederlow et al. “Low Frequency Noise Considerations for CMOS Analog Circuit Design” Proceedings of the 2005 Int. Conf. on Noise and Fluctuations (ICNF). p. 703 (2005).
R Brederlow, J Koh and R Thewes. “A physics-based low frequency noise model for MOSFETs under periodic large signal excitation” Solid-State El., 50, p. 668 (2006).
I Bloom and Y Nemirovsky. “1/f noise reduction of metal‐oxide‐semiconductor transistors by cycling from inversion to accumulation” Appl Phys Lett, 58, p.1664 (1991).
B Dierickx and E Simoen. “The decrease of “random telegraph signal” noise in metal‐oxide‐semiconductor field‐effect transistors when cycled from inversion to accumulation”. J Appl Phys, 71, p. 2028 (1992).
M Ertürk, T Xia and W Clark “Gate voltage dependence of mosfet 1/f noise statistics” IEEE Elec Dev Let, 28 p. 812 (2007).
A van der Wel et al. “Relating random telegraph signal noise in metal-oxide-semiconductor transistors to interface trap energy distribution” Appl Phys Lett., 87, p. 183507 (2005).
S Machlup, “Noise in semiconductors: spectrum of a twoparameter random signal” J Appl Phys, 35, p. 341 (1954).
A Roy and C Enz, “Analytical modeling of large-signal cyclo-stationary low-frequency noise with arbitrary periodic input”, IEEE Trans. Electron Dev., 54, p.2537 (2007).
M Kirton and M Uren “Noise in solid-state microstructures: a new perspective on individual defects, interface states and low-frequency (1/ƒ) noise” Adv. in Phys., 38, p. 367 (1989).
S Ekbote et al., “45nm low-power CMOS SoC technology with aggressive reduction of random variation for SRAM and analog transistors”, VLSI Tech. Symp., p. 160 (2008).
V Camargo et al. “Impact of rdf and rts on the performance of sram cells” J. of Comput. Electronics, p. 122 (2010).
K.K. Hung et al. “A physics-based mosfet noise model for circuit simulators” IEEE Trans. Electron Dev., 37 p. 1323 (1990).
T. Sato, et al., “A device array for efficient bias temperature instability measurements,” ESSDERC, pp. 143–146, 2011.
W. Wang et al. “Compact modeling and simulation of circuit reliability for 65 nm CMOS technology,” IEEE Trans. Dev. Mat. Reliab., 7, p. 509 (2007).
R da SILVA and G Wirth. “Logarithmic behavior of the degradation dynamics of metal oxide semiconductor devices”, Journal of Statistical Mechanics, v. P04025, p. 01 (2010).
G Wirth, R da Silva, and B Kaczer “Statistical model for mosfet bias temperature instability component due to charge trapping” IEEE Trans. on Electron Dev., 58, p.2743 (2011).
T. L. Tewksbury and H.-S. Lee, “Characterization, modeling and minimization of transient threshold voltage shifts in MOSFETs” IEEE J. Solid-State Circ., 29, p. 239 (1994).
D. K. Schroder, “Negative bias temperature instability: What do we understand?” Microel. Reliab., 47, p. 841 (2007).
V. Huard et al. “NBTI degradation: From Transistor to SRAM Arrays,” Proc. Int. Rel. Phys. Symp., p. 289 (2008).
S. E. Rauch, “Review and reexamination of reliability effects related to NBTI statistical variations” IEEE Trans Dev. Mat. Rel., 7, p. 524 (2007).
M.A. Alam et al. “A comprehensive model for pmos nbti degradation: recent progress” Microel. Reliab. p. 853 (2007).
B. Kaczer et al. “NBTI from the perspective of defect states with widely distributed times,” Proc. Int. Rel. Phys. Symp., p. 55 (2009).
Reisinger et al. “The statistical analysis of individual defects constituting NBTI and its implications for modeling DC- and AC-stress” Proc. Int. Rel. Phys. Symp., p.7 (2010).
V. Huard et al. “New characterization and modeling approach for NBTI degradation from transistor to product level”. Int Electron Dev Meeting, p. 797 (2007).
T Grasser and B Kaczer, “Evidence That Two Tightly Coupled Mechanisms Are Responsible for Negative Bias Temperature Instability in Oxynitride MOSFETs”, IEEE Trans. on Electron Dev., 56, p. 1056 (2009).
T. Grasser et al. “Switching oxide traps as the missing link between negative bias temperature instability and random telegraph noise”, Int. Electron Dev. Meeting, p. 729 (2009).
B. Kaczer et al. “Ubiquitous Relaxation in BTI stressing—New Evaluation and Insights”, Proc. Int. Reliab. Phys. Symp., p. 20 (2008).
Z. Liu, B. W. McGaughy, and J. Z. Ma, “Design tools for reliability analysis,” DAC – Desing Aut. Conf., p. 182 (2006).
M. Denais et al. “On-the-fly characterization of nbti in ultra-thin gate oxide pmosfets” Int. Elec. Dev. Meet., p. 109 (2004).
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Wirth, G., Cao, Y., Velamala, J.B., Sutaria, K.B., Sato, T. (2014). Charge Trapping in MOSFETS: BTI and RTN Modeling for Circuits. In: Grasser, T. (eds) Bias Temperature Instability for Devices and Circuits. Springer, New York, NY. https://doi.org/10.1007/978-1-4614-7909-3_29
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DOI: https://doi.org/10.1007/978-1-4614-7909-3_29
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