MAHA Hardware Architecture

  • Somnath Paul
  • Swarup Bhunia


In the previous chapter, the architecture and operation for a MBC based generic reconfigurable framework was discussed in details. In this chapter, the focus is on a malleable hardware accelerator which leverages the memory based computing model for on-demand computation in an existing memory architecture. The accelerator is referred to as MAHA which stands for Malleable Hardware Accelerator. The idea is to equip existing memory architectures with additional logic which would allow a storage-only system to be transformed into a hardware reconfigurable platform on demand. This chapter describes the hardware architecture of the MAHA framework and steps for instrumenting an existing memory architecture to realize the same. Instrumentation means the design-time modifications which would allow the memory to act as a reconfigurable framework on demand.


Reconfiguration Framework Custom Datapath Normal Memory Operation Subarray Memory Array 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


  1. 1.
  2. 2.
    R. Sangireddy, H. Kim, A.K. Somani, “Low-power high-performance reconfigurable computing cache architectures”. IEEE Trans. Comput. 53(10), (2004)Google Scholar
  3. 3.
    K.T. Park et al., “A 45nm 4Gb 3-Dimensional Double-Stacked Multi-Level NAND Flash Memory with Shared Bitline Structure”, in Intl. Solid-State Circuits Conference, 2008Google Scholar
  4. 4.
    B.V. Essen, R. Panda, A. Wood, C. Ebeling, S. Hauck, “Energy-Efficient Specialization of Functional Units a Coarse-Grained Reconfigurable Array”, in Intl. Symp. on FPGAs, 2011Google Scholar
  5. 5.
    [Online], “Mosaic Developing power-efficient coarse-grained reconfigurable architectures and tools”.
  6. 6.
    H. Singh, M. Lee, G. Lu, F.J. Kurdahi, N. Bagherzadeh, E.M. Chaves Filho, “MorphoSys: an integrated reconfigurable system for data-parallel and computation-intensive applications”. IEEE Trans. Comput. 49(5), 465–481 (2000)CrossRefGoogle Scholar
  7. 7.
    R. Hartenstein, “A Decade of Reconfigurable Computing: A Visionary Retrospective”, in Design, Automation and Test in Europe (DATE), 642–649, (2001)Google Scholar
  8. 8.
    I. Kuon, J. Rose, “Measuring the gap between FPGAs and ASICs”. IEEE Trans. Comput. Aided Des. Integrat. Circ. Syst. 26(2), (2007)Google Scholar
  9. 9.
    G. Lemieux, D. Lewis, “Circuit Design of Routing Switches”, in Intl. Symp. on FPGAs, 2002Google Scholar

Copyright information

© Springer Science+Business Media New York 2014

Authors and Affiliations

  • Somnath Paul
    • 1
  • Swarup Bhunia
    • 2
  1. 1.Intel LabsHillsboroUSA
  2. 2.Department of EECSCase Western Reserve UniversityClevelandUSA

Personalised recommendations