Abstract
In the previous chapter, the architecture and operation for a MBC based generic reconfigurable framework was discussed in details. In this chapter, the focus is on a malleable hardware accelerator which leverages the memory based computing model for on-demand computation in an existing memory architecture. The accelerator is referred to as MAHA which stands for Malleable Hardware Accelerator. The idea is to equip existing memory architectures with additional logic which would allow a storage-only system to be transformed into a hardware reconfigurable platform on demand. This chapter describes the hardware architecture of the MAHA framework and steps for instrumenting an existing memory architecture to realize the same. Instrumentation means the design-time modifications which would allow the memory to act as a reconfigurable framework on demand.
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References
[Online], “CACTI 5.1”. http://www.hpl.hp.com/techreports/2008/HPL-2008-20.html
R. Sangireddy, H. Kim, A.K. Somani, “Low-power high-performance reconfigurable computing cache architectures”. IEEE Trans. Comput. 53(10), (2004)
K.T. Park et al., “A 45nm 4Gb 3-Dimensional Double-Stacked Multi-Level NAND Flash Memory with Shared Bitline Structure”, in Intl. Solid-State Circuits Conference, 2008
B.V. Essen, R. Panda, A. Wood, C. Ebeling, S. Hauck, “Energy-Efficient Specialization of Functional Units a Coarse-Grained Reconfigurable Array”, in Intl. Symp. on FPGAs, 2011
[Online], “Mosaic Developing power-efficient coarse-grained reconfigurable architectures and tools”. http://www.cs.washington.edu/research/projects/lis/www/mosaic/
H. Singh, M. Lee, G. Lu, F.J. Kurdahi, N. Bagherzadeh, E.M. Chaves Filho, “MorphoSys: an integrated reconfigurable system for data-parallel and computation-intensive applications”. IEEE Trans. Comput. 49(5), 465–481 (2000)
R. Hartenstein, “A Decade of Reconfigurable Computing: A Visionary Retrospective”, in Design, Automation and Test in Europe (DATE), 642–649, (2001)
I. Kuon, J. Rose, “Measuring the gap between FPGAs and ASICs”. IEEE Trans. Comput. Aided Des. Integrat. Circ. Syst. 26(2), (2007)
G. Lemieux, D. Lewis, “Circuit Design of Routing Switches”, in Intl. Symp. on FPGAs, 2002
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Paul, S., Bhunia, S. (2014). MAHA Hardware Architecture. In: Computing with Memory for Energy-Efficient Robust Systems. Springer, New York, NY. https://doi.org/10.1007/978-1-4614-7798-3_8
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DOI: https://doi.org/10.1007/978-1-4614-7798-3_8
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