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Computing with Memory for Energy-Efficient Robust Systems

  • Somnath Paul
  • Swarup Bhunia

Table of contents

  1. Front Matter
    Pages i-xiii
  2. Introduction

    1. Front Matter
      Pages 1-1
    2. Somnath Paul, Swarup Bhunia
      Pages 3-9
    3. Somnath Paul, Swarup Bhunia
      Pages 11-27
    4. Somnath Paul, Swarup Bhunia
      Pages 29-34
  3. Memory Based Computing: Overview

    1. Front Matter
      Pages 35-35
    2. Somnath Paul, Swarup Bhunia
      Pages 37-40
    3. Somnath Paul, Swarup Bhunia
      Pages 41-46
    4. Somnath Paul, Swarup Bhunia
      Pages 47-50
  4. Hardware Framework

    1. Front Matter
      Pages 51-51
    2. Somnath Paul, Swarup Bhunia
      Pages 53-63
    3. Somnath Paul, Swarup Bhunia
      Pages 65-76
  5. Software Framework

    1. Front Matter
      Pages 77-77
    2. Somnath Paul, Swarup Bhunia
      Pages 79-89
    3. Somnath Paul, Swarup Bhunia
      Pages 91-104
  6. MBC Design Space Exploration

    1. Front Matter
      Pages 105-105
    2. Somnath Paul, Swarup Bhunia
      Pages 119-124
    3. Somnath Paul, Swarup Bhunia
      Pages 125-136
    4. Somnath Paul, Swarup Bhunia
      Pages 137-143
  7. Off-Chip Hardware Acceleration Using MBC

    1. Front Matter
      Pages 145-145
    2. Somnath Paul, Swarup Bhunia
      Pages 147-156
    3. Somnath Paul, Swarup Bhunia
      Pages 157-164
    4. Somnath Paul, Swarup Bhunia
      Pages 165-176
  8. Improving Reliability of Operations in MBC

    1. Front Matter
      Pages 177-177
    2. Somnath Paul, Swarup Bhunia
      Pages 179-193
    3. Somnath Paul, Swarup Bhunia
      Pages 195-208
  9. Somnath Paul, Swarup Bhunia
    Pages 209-210

About this book

Introduction

This book analyzes energy and reliability as major challenges faced by designers of computing frameworks in the nanometer technology regime.  The authors describe the existing solutions to address these challenges and then reveal a new reconfigurable computing platform, which leverages high-density nanoscale memory for both data storage and computation to maximize the energy-efficiency and reliability. The energy and reliability benefits of this new paradigm are illustrated and the design challenges are discussed. Various hardware and software aspects of this exciting computing paradigm are described, particularly with respect to hardware-software co-designed frameworks, where the hardware unit can be reconfigured to mimic diverse application behavior.  Finally, the energy-efficiency of the paradigm described is compared with other, well-known reconfigurable computing platforms.

 ·         Introduces new paradigm for hardware reconfigurable frameworks, which leverages dense memory array as a malleable resource, which can be used for information storage as well as computation;

·         Merges spatial and temporal computing to minimize interconnect overhead and achieve better scalability compared to state-of-the-art reconfigurable computing platforms;

·         Enables efficient mapping of diverse data-intensive applications from domains of signal processing, multimedia and security applications.

Keywords

Energy-efficient Computing Energy-efficient FPGA Energy-efficient GPU Energy-efficient Reconfigurable Hardware Energy-efficient System Design FPGA Low Power Circuit Design Low Power System Design Memory-based Computing Reconfigurable Computing Reliable Computing

Authors and affiliations

  • Somnath Paul
    • 1
  • Swarup Bhunia
    • 2
  1. 1.Intel LabsHillsboroUSA
  2. 2.Department of EECSCase Western Reserve UniversityClevelandUSA

Bibliographic information

  • DOI https://doi.org/10.1007/978-1-4614-7798-3
  • Copyright Information Springer Science+Business Media New York 2014
  • Publisher Name Springer, New York, NY
  • eBook Packages Engineering
  • Print ISBN 978-1-4614-7797-6
  • Online ISBN 978-1-4614-7798-3
  • Buy this book on publisher's site
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