Advertisement

A Memory Based Generic Reconfigurable Framework

  • Somnath Paul
  • Swarup Bhunia
Chapter
  • 731 Downloads

Abstract

This chapter describes the hardware architecture for MBC based stand alone reconfigurable computing framework. It first lays down the requirement for a generic reconfigurable framework and how a fully-spatial computing frameworks addresses those requirements. Next it describes the spatio-temporal MBC model and explains how it can be used as a generic reconfigurable framework. The μ-architecture for each computing unit in the MBC framework is then described in detail. Next, it illustrates with examples, how multiple computing units of the MBC framework communicate with each other via a time-multiplexed programmable interconnect. Attention has been particularly given to explaining the synchronization among multiple LUT evaluations mapped to the same or different computing units in the MBC framework.

Keywords

Programmable Interconnect Schedule Table Pipe Stage Operand Selection Mapping Table 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

References

  1. 1.
    J. Rose, R.J. Francis, D. Lewis, P. Chow, “Architecture of field programmable gate arrays: The effect of logic functionality on area efficiency”. IEEE J. Solid State Circ. 25(5), (1990)Google Scholar
  2. 2.
  3. 3.
    J.H. Tseng, K. Asanovic, “Banked Multiported Register Files for High-Frequency Superscalar Microprocessor”, in Intl. Symp. on Computer Architecture, 2003Google Scholar

Copyright information

© Springer Science+Business Media New York 2014

Authors and Affiliations

  • Somnath Paul
    • 1
  • Swarup Bhunia
    • 2
  1. 1.Intel LabsHillsboroUSA
  2. 2.Department of EECSCase Western Reserve UniversityClevelandUSA

Personalised recommendations