A Memory Based Generic Reconfigurable Framework

  • Somnath Paul
  • Swarup Bhunia


This chapter describes the hardware architecture for MBC based stand alone reconfigurable computing framework. It first lays down the requirement for a generic reconfigurable framework and how a fully-spatial computing frameworks addresses those requirements. Next it describes the spatio-temporal MBC model and explains how it can be used as a generic reconfigurable framework. The μ-architecture for each computing unit in the MBC framework is then described in detail. Next, it illustrates with examples, how multiple computing units of the MBC framework communicate with each other via a time-multiplexed programmable interconnect. Attention has been particularly given to explaining the synchronization among multiple LUT evaluations mapped to the same or different computing units in the MBC framework.


Programmable Interconnect Schedule Table Pipe Stage Operand Selection Mapping Table 
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Copyright information

© Springer Science+Business Media New York 2014

Authors and Affiliations

  • Somnath Paul
    • 1
  • Swarup Bhunia
    • 2
  1. 1.Intel LabsHillsboroUSA
  2. 2.Department of EECSCase Western Reserve UniversityClevelandUSA

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