Mitigating the Effect of Runtime-Failures in MBC Frameworks

  • Somnath Paul
  • Swarup Bhunia


In nanoscale technologies, memories are vulnerable to both parametric failures, as well as, runtime failures induced by “soft errors” such as voltage, or thermal noise and aging effects. This chapter addresses the runtime failures in on-chip memories induced by “soft errors”. Conventionally such runtime errors are addressed using single error correction double error detection (SECDED) codes. However, these codes have very limited correction capability, making them inefficient to protect memory in scaled technologies (sub-45 nm), which are particularly vulnerable to multiple-bit failures (Hareland et al. Characterization of Multi-bit Soft Error events in advanced SRAMs, Intl. Electron Devices Meeting, 2003; Osada et al. IEEE J Solid State Circ 39(5), 2004). The requirement to tolerate multi-bit failures is accentuated by inter-die and intra-die variation in memory blocks which increases the vulnerability towards runtime failures. This chapter explores architectural modifications and a novel reconfigurable error-control coding (ECC) technique which together can be extremely effective in protecting on-chip memories against runtime failures.


Memory Block Soft Error Runtime Error SRAM Cell Dynamic Voltage Scaling 
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Copyright information

© Springer Science+Business Media New York 2014

Authors and Affiliations

  • Somnath Paul
    • 1
  • Swarup Bhunia
    • 2
  1. 1.Intel LabsHillsboroUSA
  2. 2.Department of EECSCase Western Reserve UniversityClevelandUSA

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