Advertisement

Design Space Exploration for MAHA Framework

  • Somnath Paul
  • Swarup Bhunia
Chapter
  • 726 Downloads

Abstract

Similar to the design space exploration for MBC based generic reconfigurable framework, critical decisions are required to select the design parameters for the MAHA framework. The choice is complicated by the fact, that the design choice should have minimal impact on the normal operation for the memory array which has been instrumented to form the MAHA framework. Moreover, the programmable interconnect resources are more restricted in case of MAHA and choice of interconnect hierarchy affects the success of mapping different applications to this framework. In addition, the size of the custom datapath component present in each MLB in a MAHA architecture needs to be ascertained. Similar to the case of a generic reconfigurable framework, the MBC software flow explores both logic and interconnect components and arrives at a design choice with minimum overhead but with a performance that satisfies the requirement.

Keywords

Discrete Cosine Transform Discrete Wavelet Transform Advance Encryption Standard Function Table Parallel Operation 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

References

  1. 1.
    T. Good, M. Benaissa, “692-nW advanced encryption standard (AES) on a 0.13 μ m CMOS”. IEEE Trans. Very Large Scale Integrat. Syst. (2009)Google Scholar
  2. 2.
    [Online], “Secure Hash Algorithm - 1”. http://en.wikipedia.org/wiki/SHA-1
  3. 3.
    H. Singh, M. Lee, G. Lu, F.J. Kurdahi, N. Bagherzadeh, E.M. Chaves Filho, “MorphoSys: an integrated reconfigurable system for data-parallel and computation-intensive applications”. IEEE Trans. Comput. 49(5), 465–481 (2000)CrossRefGoogle Scholar
  4. 4.
    [Online], http://vigir.missouri.edu/~gdesouza/Research/ColorCCD/ColorInterpolatio%n.pdfGoogle Scholar
  5. 5.
    U. Meyer-Baese, “Digital Signal Processing with Field Programmable Gate Arrays” (Springer, Heidelberg, 2007)Google Scholar
  6. 6.
    K. Andra, C. Chakrabarti, T. Acharya, “A VLSI architecture for lifting-based forward and inverse wavelet transform”. IEEE Trans. Signal Process., 966–977 (2002)Google Scholar
  7. 7.
    [Online], “Smith-Waterman Algorithm”. http://en.wikipedia.org/wiki/Smith--Waterman_algorithm
  8. 8.
    K. Nigam, J. Lafferty, A. McCallum, “Using Max Entropy for Text Classification”, in Intl. Joint Conf. on Artifical Intelligence, 1999Google Scholar
  9. 9.
    [Online], “Predictive Technology Model”. http://ptm.asu.edu/

Copyright information

© Springer Science+Business Media New York 2014

Authors and Affiliations

  • Somnath Paul
    • 1
  • Swarup Bhunia
    • 2
  1. 1.Intel LabsHillsboroUSA
  2. 2.Department of EECSCase Western Reserve UniversityClevelandUSA

Personalised recommendations