Abstract
In the era of nanoscale technologies, computing systems are faced with a set of common challenges, namely energy-efficiency and reliability. This challenge applies to varieties of computing systems namely software programmable general-purpose processors, hardware reconfigurable computing frameworks and application-specific custom hardware. As demonstrated by numerous prior works from both industry and academia, an energy-efficient and reliable VLSI system in nanoscale technologies is actually an ensemble of the different computing approaches mentioned above. In this chapter, we discuss each of the challenges in detail, particularly in the context of the emerging workloads for modern VLSI systems.
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References
O. Shacham et al., “Rethinking Digital Design: Why Design Must Change”, in Intl. Symp. Microarchitecture, 2010
M. Bohr, “Silicon Technology Leadership for the Mobility Era”. http://www.intel.com/content/dam/www/public/us/en/documents/presentation/silicon-technology-leadership-presentation.pdf
F. Pollack, “New Microarchitecture Challenges in the Coming Generations of CMOS Process Technologies”, in Intl. Symp. on Microarchitecture, 1999
G.M. Amdahl, “Validity of the Single Processor Approach to Achieving Large-Scale Computing Capabilities”, in AFIPS, 1967
X. Vera-Raimat, “DFx for Terascale Reliable Processors”. http://www.cse.psu.edu/~yuanxie/ISCA10-WTAI/Reliability-Vera-Intel.pdf
P. Kogge et al., “ExaScale Computing Study: Technology Challenges in Achieving Exascale Systems”. http://www.cse.nd.edu/Reports/2008/TR-2008-13.pdf
S. Paul, F. Cai, X. Zhang, S. Bhunia, “Reliability-driven ECC allocation for multiple bit error resilience in processor cache”. IEEE Trans. Comput. 60(1), 20–34 (2011)
S. Mukhopadhyay, H. Mahmoodi, K. Roy, “Modeling of failure probability and statistical design of SRAM array for yield enhancement in nanoscaled CMOS”. IEEE Trans. Comput. Aided Des. Integrat. Circ. Syst. 24(12), 1859–1880 (2005)
“International Technology Roadmap for Semiconductors 2001 Edition: Interconnect”. http://www.itrs.net/Links/2001ITRS/Interconnect.pdf
[Online], “ITRS 2007: Interconnect”. http://www.itrs.net/links/2007itrs/home2007.htm
[Online], “Future processing: Extreme scale”. http://www.hpcuserforum.com/EU/downloads/DARPAExtremscaleHarrod_ACS_Brief_01709.pdf
E.S. Chung, P.A. Milder, J.C. Hoe, K. Mai, “Single-Chip Heterogeneous Computing: Does the Future Include Custom Logic, FPGAs, and GPGPUs? in Intl. Symp. on Microarchitecture, 2010
[Online], “The Berkeley Intelligent RAM (IRAM) Project”. http://iram.cs.berkeley.edu/
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Paul, S., Bhunia, S. (2014). Challenges in Computing for Nanoscale Technologies. In: Computing with Memory for Energy-Efficient Robust Systems. Springer, New York, NY. https://doi.org/10.1007/978-1-4614-7798-3_1
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DOI: https://doi.org/10.1007/978-1-4614-7798-3_1
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