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Circuits and Systems for Multi-Channel Neural Recording

Chapter

Abstract

This chapter presents three different circuits and systems architectures enabling multichannel neural recording. These systems preserve the temporal information of the recording sites by avoiding time -multiplexed operation of the ADC. Moreover, various system-level original concepts are introduced that improve trade-offs between noise, power, and silicon area. Oversampling is introduced in Sect. 5.2 as a useful technique to improve the noise efficiency factor (NEF) at system level. Since the total power consumption is dominated by low-noise front-end amplifiers, any increase in the power consumption of the ADC due to the oversampling, has a negligible impact on the overall power consumption of the system. Nevertheless, the input-referred noise is reduced using an oversampling ADC, as the integrated noise bandwidth is reduced by increasing the oversampling ratio, which results in an improved noise efficiency factor (NEF). A 16-channel neural action potential recording IC is presented as a proof-of-concept prototype. A closed-loop gain of 60 dB in the action potential band is achieved by cascading differential gain -stages utilizing a novel common-mode feedback (CMFB) circuit. An oversampling delta modulator (DM) serves as an ADC in order to improve the NEF of the recording system. Moreover, in-site compression is achieved by converting the temporal difference of the input neural signal. The DM employs a novel dynamic voltage comparator with a partial reset preamplifier, which enhances the mean time to failure of the modulator. The proposed architecture is fabricated in a \(0.18\,\upmu \mathrm{{m}}\) CMOS technology. The 16-channel system consumes \(220\,\upmu \mathrm{{W}}\) from a 1.2 V power supply. The SNDR is measured at 28.3 and 35.9 dB at the modulator and demodulator outputs, respectively. The total integrated in-band input-referred noise is measured at \(2.8\,\upmu \mathrm{{V}}_{\mathrm{{rms}}}\), which corresponds to \(\mathrm{{NEF}}=4.6\) for the entire system. Section 5.3 introduces the application of algebraic coding to a multi-channel neural recording system. Walsh-Hadamard coding enables back-end hardware sharing between recording channels employing a single ADC, thereby avoiding time -multiplexing. A single ADC converts the analog superposition of multiple channels. Thus, the dynamic range of the ADC is effectively shared between channels benefiting from the sparsity characteristics of the channels in space domain . Also, noise coupling, interference, and crosstalk are reduced, thanks to the low-impedance and low-swing wired summation of the channels in the analog domain . A 16-channel recording system is developed as a test vehicle. This system provides 60 dB of accurate gain for signal amplification and is programmable by steps of 19 dB. A single 10-bit SAR ADC is used for data conversion. The system is implemented in a \(0.18\,\upmu \mathrm{{m}}\) CMOS technology and occupies a silicon area of \(1.99\,\mathrm{{mm}}^{2}\). Placing the ADC outside of the sensor plane enables reducing the channel’s pitch, with respect to the standard value of \(400\,\upmu {\mathrm{{m}}}\) which is used in Utah’s MEA. The input-referred noise of a single channel integrated from 100 Hz to 100 kHz is simulated at \(4.1\,\upmu \mathrm{{V}}_{\mathrm{{rms}}}\) while consuming \(359\,\upmu \mathrm{{W}}\) from a 1.2 V power supply, which results in a system-level NEF of 5.6. Finally, a 64-channel neural recording system-on-a-chip (SoC) is presented in Sect. 5.4. The system is composed of an on-chip half-wave voltage rectifier, low-voltage bandgap reference circuit, LDO voltage regulator, on-chip reference generator, 64-channel mixed-signal core with dedicated 8-bit SAR ADC per channel, and an on-chip digital ASIC for packet generation , scrambling, and synchronization. A programmable power management technique is proposed which enables dynamic power scaling (DPS) of the mixed-signal core. Applying the DPS technique, the power consumption of each individual channel is reduced by 20.4 % which is equivalent to a reduction of 16 % in the total power consumption of the analog/mixed-mode front-end. The total power dissipation of the SoC is measured at 3.26 mW from a 1.2 V power supply. The SoC is fabricated in a \(0.18\,\upmu \mathrm{{m}}\) CMOS technology and occupies an active silicon area of \(17.5\,\mathrm{{mm}}^{2}\).

Keywords

Device Under Test Silicon Area Variable Gain Amplifier Delta Modulator Operational Transconductance Amplifier 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

References

  1. 1.
    Abdelhalim K, Genov R (2001) 915-MHz wireless 64-channel neural recording SoC with programmable mixed-signal FIR filters. In: Proceedings of European Solid State Circuit Conference, pp 223–226, Sept 2011Google Scholar
  2. 2.
    Alzaher HA, Elwan HO, Ismaeil M (2002) A CMOS highly linear channel-select filter for 3G multistandard integrated wireless receivers. IEEE J Solid-State Circuits 37(1):27–37CrossRefGoogle Scholar
  3. 3.
    Amico S, Conta M, Baschirotto A (2006) A 4.1 mW 10 MHz fourth-order source-follower-based continuous-time filter with 79 dB DR. IEEE J Solid-State Circuits 41(12):2713–2719CrossRefGoogle Scholar
  4. 4.
    Anderson TO (1972) Optimum control logic for successive approximation AD converters. Comput Design 11(7):8186Google Scholar
  5. 5.
    Aziz JNY et al (2009) 256-channel neural recording and delta compression microsystem with 3D electrodes. IEEE J Solid-State Circuits 44(3):995–1005CrossRefGoogle Scholar
  6. 6.
    Blahut RE (2003) Algebraic codes for data transmission. Cambridge University Press, CambridgeMATHCrossRefGoogle Scholar
  7. 7.
    Chae MS, Liu W, Sivaprakasam M (2008) Design optimization for integrated neural recording systems. IEEE J Solid-State Circuits 43(9):1931–1939CrossRefGoogle Scholar
  8. 8.
    Chen Y et al (2009) Split capacitor DAC mismatch calibration in successive approximation ADC. In: Custom Integrated Circular Conference (CICC), pp 279–282, Sept 2009Google Scholar
  9. 9.
    Chen X, Yu Z, Hoyos S, Sadler B, Martinez JS (2011) A sub-Nyquist rate sampling receiver exploiting compressive sensing. IEEE Trans Circuits Syst-I 58(3):507–520MathSciNetCrossRefGoogle Scholar
  10. 10.
    Chen F, Chnadrakasan A, Stojanović V (2012) Design and analysis of a hardware-efficient compressed sensing architecture for data compression in wireless sensors. IEEE J Solid-State Circuits 47(3):744–756CrossRefGoogle Scholar
  11. 11.
    Driscoll S, Shenoy KV, Meng TH (2011) Adaptive resolution ADC array for an implantable neural sensor. IEEE Trans Biomed Circuits Syst 5(2):120–130CrossRefGoogle Scholar
  12. 12.
    Gao H, Walker RM, Nuyujukian P, Mikanawa KA, Shenoy KV, Murmann B, Meng TH (2012) HermesE: A 96-channel full data rate direct neural interface in \(0.13\,\upmu {\rm {m}}\) CMOS. IEEE J Solid-State Circuits 47(4):1043–1055CrossRefGoogle Scholar
  13. 13.
    Ginsburg BP, Chandrakasan AP (2007) 500 MS/s 5-bit ADC in 65 nm CMOS with split capacitor array DAC. IEEE J Solid-State Circuits 42(4):739–747CrossRefGoogle Scholar
  14. 14.
    Harrison RR, Charles C (2003) A low-power low-noise CMOS amplifier for neural recording applications. IEEE J Solid-State Circuits 38(6):958–965CrossRefGoogle Scholar
  15. 15.
    Harrison RR et al (2007) A low-power integrated circuit for a wireless 100-electrode neural recording system. IEEE J Solid-State Circuits 42(1):123–133CrossRefGoogle Scholar
  16. 16.
    Haseloff E (2000) Latch-up, ESD, and other phenomena, application note. In: Texas instrument. http://www.ti.com/lit/an/slya014a/slya014a.pdf
  17. 17.
  18. 18.
    Inan OT, Kovacs G (2010) An \(11\,\upmu {\rm {W}}\), two-electrode transimpedance biosignal amplifier with active current feedback stabilization. IEEE Trans Biomed Circuits Syst 4(2):93–100CrossRefGoogle Scholar
  19. 19.
    Liu CC, Chang SJ, Huang GY, Lin YZ (2007) A 65-fJ/conversion-step 0.9 V 200 kS/s rail-to-rail 8-bit successive approximation ADC. IEEE J Solid-State Circuits 42(10):2161–2168CrossRefGoogle Scholar
  20. 20.
    Liu CC, Chang SJ, Huang GY, Lin YZ (2010) A 10-bit 50 MS/s SAR ADC with a monotonic capacitor switching procedure. IEEE J Solid-State Circuits 45(4):731–740CrossRefGoogle Scholar
  21. 21.
    Majidzadeh V et al (2010) A (\(256\times 256\)) Pixel 76.7 mW CMOS imager/compressor based on real-time in-pixel compressive sensing. Proc IEEE Int Symp Circuits Systems (ISCAS 2010) 1(1):2956–2959CrossRefGoogle Scholar
  22. 22.
    Majidzadeh V, Schmid A, Leblebici Y (2011) Energy efficient low-noise neural recording amplifier with enhanced noise efficiency factor. IEEE Trans Biomed Circuits Syst 5(3):262–271CrossRefGoogle Scholar
  23. 23.
    Mollazadeh M, Murari K, Cauwenberghs G, Thakor N (2009) Micropower CMOS integrated low-noise amplification, filtering, and digitization of multimodal neuropotentials. IEEE Trans Biomed Circuits Syst 3(1):1–10CrossRefGoogle Scholar
  24. 24.
    Muller R, Gambini S, Rabaey J (2011) A \(0.013\,{\rm {mm}}^{2} 5\,\upmu {\rm {W}}\) DC-DC-coupled neural signal acquisition IC with 0.5 V supply. ISSCC Dig Tech Papers, pp 302–303Google Scholar
  25. 25.
    Murmann B (1997) ADC Performance Survey 1997–2011. http://www.stanford.edu/murmann/adcsurvey.html
  26. 26.
    Python D, Enz C (2001) A micropower class-AB CMOS log-domain filter for DECT application. IEEE J Solid-State Circuits 36(7):1067–1075CrossRefGoogle Scholar
  27. 27.
    Rabei S, Wooley BA (1997) A 1.8 V digital-audio sigma-delta modulator in \(0.8\,\mu {\rm {m}}\) CMOS. IEEE J Solid-State Circuits 32(6):783–796CrossRefGoogle Scholar
  28. 28.
    Rai S, Holleman J, Pandey JN, Zhang F, Otis B (2009) A \(500\,\upmu {\rm {W}}\) neural tag with \(2\,\upmu {\rm {V}}_{{\rm {rms}}}\) AFE and frequency-multiplying MICS/ISM FSK transmitter. ISSCC Dig Tech Papers, pp 212–213, Feb 2009Google Scholar
  29. 29.
    Razavi B (1995) Principles of data conversion system design. IEEE press, New YorkGoogle Scholar
  30. 30.
    Saberi M, Lotfi R, Mafinezhad K, Serdijn W (2011) Analysis of power consumption and linearity in capacitive digital-to-analog converters used in successive approximation ADCs. IEEE Trans Circuits Syst-I 58(8):1736–1748MathSciNetCrossRefGoogle Scholar
  31. 31.
    Schreier R, Temes GC (2005) Understanding delta-sigma data converters. IEEE press, New JerseyGoogle Scholar
  32. 32.
    Sundström T, Murmann B, Svensson C (March 2009) Power dissipation bounds for high-speed Nyquist analog-to-digital converters. IEEE Trans Circuits Syst-I 56(3):509–518CrossRefGoogle Scholar
  33. 33.
    Tajalli A (2010) Power-performance scalable integrated circuit design using subthreshold MOS. PhD Thesis no 4810, EPFLGoogle Scholar
  34. 34.
    Tajalli A, Leblebici Y (2008) Implementing ultra-high-value floating tunable CMOS resistors. Electron Lett 44(5):349–350CrossRefGoogle Scholar
  35. 35.
    Tajalli A, Leblebici Y (2010) Nanowatt range folding-interpolating ADC using subthreshold source-coupled circuits. J Low-Power Electron 6:211–217CrossRefGoogle Scholar
  36. 36.
    Tajalli A, Leblebici A (2009) Widely-tunable and power-scalable MOSFET-C Filter operating in subthreshold. In: Proceedings of the Custom Integrated Circuits Conference (CICC), IEEE, pp 593–596, Sept 2009Google Scholar
  37. 37.
    Tavakoli M, Turicchia L, Sarpeshkar R (2010) An ultra-low-power pulse oximeter implemented with an energy-efficient transimpedance amplifier. IEEE Trans Biomed Circuits Syst 4(1):27–38CrossRefGoogle Scholar
  38. 38.
    Wessberg J et al (2000) Real-time prediction of hand trajectory by ensembles of cortical neurons in primates. Nature 408:361–365CrossRefGoogle Scholar
  39. 39.
    Yan W, Zimmermann H (2008) Continuous-time common-mode feedback circuit for applications with large output swing and high output impedance. In: IEEE workshop on design and diagnostics of electronics circuits and systems, (DDECS’08), pp 1–5, 2008Google Scholar
  40. 40.
    Yoshizawa A, Tsividis Y (2002) Anti-blocker design techniques for MOSFET-C filters for direct conversion receivers. IEEE J Solid-State Circuits 37(3):357–364CrossRefGoogle Scholar

Copyright information

© Springer Science+Business Media New York 2013

Authors and Affiliations

  1. 1.Swiss Federal Institute of TechnologyLausanneSwitzerland
  2. 2.Swiss Federal Institute of TechnologyLausanneSwitzerland

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