Circuit Elements Required for Neural Systems

Abstract

This chapter begins by explaining the underlying physics of a neural pulse, thus developing a circuit model that provides a proper pulse waveform. Key to the pulse waveform is are ion-instigated current sources that charge and discharge membrane capacitance. Significant membrane conductance and high internal series resistance serve to regulate charging, resulting in pulse propagation well below the speed of electricity metal conductors. Consequently even a short length of active dendrite provides substantial delay.

The circuit elements introduced below are backed by pulse simulations in this book’s appendix.

A short-term memory (STM) neuron has major importance and is given its own symbol. STM is modeled below to depend on dendrites that experience a shortfall of ion-instigated current leaving the interior. These dendrites are special in that they support a pulse whose width is greater than normally expected. This results in extended triggering of the soma and a burst of pulses down the axon whose duration ranges from milliseconds to seconds, depending on dendritic parameters.

Synapses are modeled as ideal electronic amplifiers with a signal that flows from input to output; they serve to connect neurons together. A transconductance, or voltage-controlled current amplifier (triangular) symbol is used for excitatory synapses, modeled as injecting positive charge into the postsynaptic region thus triggering a dendritic pulse. A nearly identical symbol, but marked to indicate negative output, is used for inhibitory synapses, the effect of which is often equivalent to injecting negative charge into a postsynaptic region. A special synapse termed a “weak” synapse was found to be helpful to a neural system and is proposed to produce but a single dendritic pulse, necessary for system timing. Lacking a weak synapse, equivalent circuits for a single pulse are available based on ordinary logic neurons and a STM neuron.

Long-term potentiation (LTP), important to long-term memory, is modeled as an excitatory postsynaptic receptor with a capacitor that traps and holds initial charge. The resulting voltage, which is assumed to be permanent, makes it easier to trigger the receptor.

Capacitance symbols also serve to denote when a dendritic pulse encounters a larger capacitive body or soma, which results in back propagations, according to simulations.

A variety of neural logic is introduced including dendritic logic, which is totally independent of synapses. Dendritic logic occurs within inhomogeneous regions, and at dendritic junctions, and is capable of arbitrary Boolean logic, including OR, AND, and XOR. The XOR indirectly permits a NOT gate. There may be thousands of dendritic logic gates in a single neuron. However, to work properly, pulses must arrive simultaneously at the points where the gates exist.

Synaptic weights are not included in the analysis below since it is assumed that a membrane either pulses or it does not. However, standardized pulses from adjacent spines may very well proceed to undergo dendritic logic.

A important variety of logic termed enabled logic occurs when dendrites contact a capacitive load, at a soma. AND/OR gates are readily possible as described below; enabled NOT gates are also possible in conjunction with inhibitory neurotransmitters. Enabled logic is less critical for timing, and is chiefly limited to somas, one per neuron.