Abstract
In all cases described so far when a packet allocated a link (or an output of a router) the connection was kept until the tail of the packet traversed the link and released its usage to other packets. This behavior was imposed by the fact that the buffers at the other side of the link (or the input of the next router) kept the control information of only one packet, thus prohibiting the interleaving of flits from different packets. This flow of packets resembles a single-lane street where cars move one after the other and even if a car wants to turn to a different direction it is obliged to wait the rest cars to pass the turning point before being able to make the turn to its preferred direction (see Fig. 6.1a). Also, this serial packet movement prohibits packet flow isolation since all traffic is inevitably mixed in the one-lane streets of the network.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
References
Becker D (2012a) Adaptive backpressure: Efficient buffer management for on-chip networks. In: IEEE ICCD
Boura YM, Das CR (1997) Performance analysis of buffering schemes in wormhole routers. IEEE Transactions on Computers 46:687–694
Dally WJ (1992) Virtual-channel flow control. IEEE Transactions on on Parallel and Distributed Systems 3(3):194–205
Dally WJ, Aoki H (1993) Deadlock-free adaptive routing in multicomputer networks using virtual channels. IEEE Trans Parallel Distrib Syst 4(4):466–475, DOI http://dx.doi.org/10.1109/71.219761
Duato J (1993) A new theory of deadlock-free adaptive routing in wormhole networks. IEEE Trans Parallel Distrib Syst 4(12):1320–1331
Grot B, Hestness J, Keckler SW, Mutlu O (2012) A QoS-Enabled On-Die Interconnect Fabric for Kilo-Node Chips. IEEE Micro 32(3)
Katevenis M, Serpanos D, Spyridakis E (1998) Credit-flow-controlled ATM for MP interconnection: the ATLAS I single-chip ATM switch. In: IEEE International Symposium on High-Performance Computer Architecture (HPCA), pp 47–56
Martin M, et al (2005) Multifacet’s general execution-driven multiprocessor simulator (gems) toolset. SIGARCH Comput Archit News 33(4):92–99
Nachiondo T, Flich J, Duato J (2006) Destination-based hol blocking elimination. In: International Conference on Parallel and Distributed Systems, IEEE Computer Society, pp 213–222
Ni N, Pirvu M, Bhuyan LN (1998) Circular buffered switch design with wormhole routing and virtual channels. In: ICCD, pp 466–473
Nicopoulos C, et al (2006) Vichar: A dynamic virtual channel regulator for network-on-chip routers. In: IEEE/ACM Intern. Symp. on Microarchitecture, pp 333–346
Park J, O’Krafka B, Vassiliadis S, Delgado-Frias J (1994) Design and evaluation of a damq multiprocessor network with self-compacting buffers. In: Proceedings of the 1994 ACM/IEEE Conference on Supercomputing, IEEE Computer Society Press, Supercomputing ’94, pp 713–722
Seitanidis I, Psarras A, Dimitrakopoulos G, Nicopoulos C (2014a) Elastistore: An elastic buffer architecture for network-on-chip routers. In: Proc. of Design Automation and Test in Europe (DATE)
Tamir Y, Frazier GL (1992) Dynamically-allocated multi-queue buffers for vlsi communication switches. IEEE Transactions on Computers 41(6):725–737
Tran AT, Baas BM (2011) RoShaQ: High-performance on-chip router with shared queues. In: IEEE ICCD, pp 232–238
Author information
Authors and Affiliations
Rights and permissions
Copyright information
© 2015 Springer Science+Business Media New York
About this chapter
Cite this chapter
Dimitrakopoulos, G., Psarras, A., Seitanidis, I. (2015). Virtual-Channel Flow Control and Buffering. In: Microarchitecture of Network-on-Chip Routers. Springer, New York, NY. https://doi.org/10.1007/978-1-4614-4301-8_6
Download citation
DOI: https://doi.org/10.1007/978-1-4614-4301-8_6
Published:
Publisher Name: Springer, New York, NY
Print ISBN: 978-1-4614-4300-1
Online ISBN: 978-1-4614-4301-8
eBook Packages: EngineeringEngineering (R0)