Abstract
Having described the flow of data on a point-to-point link (1-to-1 connection) and the implications of each design choice, in this chapter, we move one step forward and describe the operation of modules that allow many to one and many to many connections. The operation of such modules involves, besides flow control, additional operations such as allocation and multiplexing that require the addition of extra control state per input and per output.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
References
Ascia G, Catania V, Palesi M, Patti D (2008) Implementation and analysis of a new selection strategy for adaptive routing in networks-on-chip. IEEE Transactions on Computers 57(6): 809–820
Balkan A, QGang, UVishkin (2009) Mesh-of-trees and alternative interconnection networks for single-chip parallelism. IEEE Transactions on VLSI Systems 17(10):1419–1432
Duato J, Yalamanchili S, Ni LM (1997) Interconnection networks - an engineering approach. IEEE
Flich J, Duato J (2008) LBDR: Logic-Based Distributed Routing for NoCs. IEEE Computer Architecture Letters 7(1):13–16
Flich J, Mejia A, Lopez P, Duato J (2007) Region-based routing: An efficient routing mechanism to tackle unreliable hardware in networks on chip. In: Intern. Symp. on Networks on Chip (NOCS)
Galles M (1997) Spider: A high-speed network interconnect. IEEE Micro 17(1)
Huan Y, DeHon A (2012) Fpga optimized packet-switched noc using split and merge primitives. In: Int. Conf. on Field-Programmable Technology (FPT), pp 47–52
Karol M, Hluchyj M, Morgan S (1987) Input versus output queueing on a space-division packet switch. IEEE Trans on Communications COM-35(12):1374–1356
Medhi D, Ramasamy K (2007) Network Routing: Algorithms, Protocols, and Architectures. Morgan Kaufmann Publishers, an imprint of Elsevier
Moscibroda T, Mutlu O (2009) A case for bufferless routing in on-chip networks. In: Proceedings of the 36th International Symposium on Computer Architectur, IEEE
Rahimi A, Loi I, Kakoee MR, Benini L (2011) A fully-synthesizable single-cycle interconnection network for shared-l1 processor clusters. In: DATE, pp 1–6
Roca A, Flich J, Dimitrakopoulos G (2012) Desa: Distributed elastic switch architecture for efficient networks-on-fpgas. In: 22nd Inter. Conf. on Field Programmable Logic and Applications (FPL), pp 394–399
Vaidya AS, Sivasubramaniam A, Das CR (1999) LAPSES: A recipe for high performance adaptive router design. In: Proceedings of the 5th International Symposium on High Performance Computer Architecture (HPCA ’99), IEEE Computer Society, Washington, DC, USA, p 236
Author information
Authors and Affiliations
Rights and permissions
Copyright information
© 2015 Springer Science+Business Media New York
About this chapter
Cite this chapter
Dimitrakopoulos, G., Psarras, A., Seitanidis, I. (2015). Baseline Switching Modules and Routers. In: Microarchitecture of Network-on-Chip Routers. Springer, New York, NY. https://doi.org/10.1007/978-1-4614-4301-8_3
Download citation
DOI: https://doi.org/10.1007/978-1-4614-4301-8_3
Published:
Publisher Name: Springer, New York, NY
Print ISBN: 978-1-4614-4300-1
Online ISBN: 978-1-4614-4301-8
eBook Packages: EngineeringEngineering (R0)