On Designing 3-D Platforms

Abstract

Several new topologies for on-chip interconnect networks are supported by vertical integration. These three-dimensional (3-D) topologies improve the performance of an on-chip network primarily in two ways. The length of the physical links connecting the switches of the network is shorter. Additionally, the data can be routed across the on-chip network through a smaller number of switches. 3-D NoC topologies include two different types of physical links implemented with horizontal and vertical interconnects. Among others, these links exhibit differentiations in terms both of physical, as well as electrical characteristics. Though a number of topology exploration frameworks for quantifying the potential improvements from this new design paradigm, the assumptions made from the majority of them usually leads to results with considerable variation as compared to the actual 3-D platforms. On the other hand, there are only a few CAD tools for designing 3-D chips (e.g., $\mathrm{{R}}{3}$Logic [1]). Throughout this chapter we introduce a framework for quantifying the potential gains of employing this new design technology onto digital designs. In contrast to relevant approaches, which are mainly based on models from academic tools, the solution discussed here is based on Cadence toolflow [2].

This chapter was contributed by Dionysios Diamantopoulos, Kostas Siozios, George Economakos, and Dimitrios Soudris of the School of ECE, National Technical University of Athens.