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Designing 2D and 3D Network-on-Chip Architectures

  • Konstantinos Tatas
  • Kostas Siozios
  • Dimitrios Soudris
  • Axel Jantsch

Table of contents

  1. Front Matter
    Pages i-xiii
  2. Network-on-Chip Design Methodology

    1. Front Matter
      Pages 1-1
    2. Konstantinos Tatas, Kostas Siozios, Dimitrios Soudris, Axel Jantsch
      Pages 3-18
    3. Konstantinos Tatas, Kostas Siozios, Dimitrios Soudris, Axel Jantsch
      Pages 19-49
    4. Konstantinos Tatas, Kostas Siozios, Dimitrios Soudris, Axel Jantsch
      Pages 51-96
    5. Konstantinos Tatas, Kostas Siozios, Dimitrios Soudris, Axel Jantsch
      Pages 97-126
    6. Konstantinos Tatas, Kostas Siozios, Dimitrios Soudris, Axel Jantsch
      Pages 127-145
    7. Konstantinos Tatas, Kostas Siozios, Dimitrios Soudris, Axel Jantsch
      Pages 147-159
    8. Konstantinos Tatas, Kostas Siozios, Dimitrios Soudris, Axel Jantsch
      Pages 161-190
    9. Konstantinos Tatas, Kostas Siozios, Dimitrios Soudris, Axel Jantsch
      Pages 191-208
    10. Konstantinos Tatas, Kostas Siozios, Dimitrios Soudris, Axel Jantsch
      Pages 209-236
    11. Konstantinos Tatas, Kostas Siozios, Dimitrios Soudris, Axel Jantsch
      Pages 237-255
  3. Suggested Projects

    1. Front Matter
      Pages 257-257
    2. Konstantinos Tatas, Kostas Siozios, Dimitrios Soudris, Axel Jantsch
      Pages 259-265

About this book

Introduction

This book covers key concepts in the design of 2D and 3D Network-on-Chip interconnect.  It highlights design challenges and discusses fundamentals of NoC technology, including architectures, algorithms and tools.  Coverage focuses on topology exploration for both 2D and 3D NoCs, routing algorithms, NoC router design, NoC-based system integration, verification and testing, and NoC reliabilty.  Case studies are used to illuminate new design methodologies. 

·         Describes essential theory, practice and state-of-the-art applications of 2D and 3D Network-on-Chip interconnect;

·         Enables readers to exploit parallelism in processor architecture, with interconnect design that is efficient in terms of energy and performance;

·         Covers topics not available in other books, such as NoC and distributed memory organization, dynamic memory management and abstract data type support in many-core platforms, and distributed hierarchical power management.

Keywords

3D Network-on-Chip Embedded Systems Design Integrated Circuit Design Low-power Network-on-Chip Network-on-Chip Network-on-Chip Architecture Network-on-Chip Reliability NoC NoC-based System Integration

Authors and affiliations

  • Konstantinos Tatas
    • 1
  • Kostas Siozios
    • 2
  • Dimitrios Soudris
    • 3
  • Axel Jantsch
    • 4
  1. 1.Dept of Computer Science and EngineeringFrederick University School of Applied SciencesNicosiaCyprus
  2. 2.Department of Computer ScienceNational Technical University of AthensAthensGreece
  3. 3.Department of Computer ScienceNational Technical University of AthensAthensGreece
  4. 4.Department of Electronic SystemsRoyal Institute of TechnologyKistaSweden

Bibliographic information

  • DOI https://doi.org/10.1007/978-1-4614-4274-5
  • Copyright Information Springer Science+Business Media New York 2014
  • Publisher Name Springer, New York, NY
  • eBook Packages Engineering
  • Print ISBN 978-1-4614-4273-8
  • Online ISBN 978-1-4614-4274-5
  • Buy this book on publisher's site
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