Abstract
This chapter describes various aspects of power dissipation in macro blocks and IOs in a CMOS design. As described in Chap. 2, the memory macros and the IOs can have power dissipation due to switching activity, called active power, and another contribution called leakage power that represents the power without any activity in the macro.
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Notes
- 1.
Input, output or bidirectional buffers.
- 2.
The leakage power of the memory macro does depend upon various control signals which may place the memory in one of the shutdown or the low leakage modes.
- 3.
34 ohms is one of the JEDEC standard drive impedance for DDR3 [JED10].
- 4.
There is additional leakage power in the IO both with and without termination.
- 5.
40 ohms is one of the JEDEC standard drive impedance for DDR3 [JED10].
- 6.
60 ohms is one of the JEDEC standard input termination impedance for DDR3 [JED10].
- 7.
There is additional leakage power in the IO both with and without termination.
Reference
[JED10] DDR3 SDRAM Specification, JESD79-3E, July 2010.
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© 2013 Springer Science+Business Media New York
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Chadha, R., Bhasker, J. (2013). Modeling of Power in IOs and Macro Blocks. In: An ASIC Low Power Primer. Springer, New York, NY. https://doi.org/10.1007/978-1-4614-4271-4_3
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DOI: https://doi.org/10.1007/978-1-4614-4271-4_3
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Print ISBN: 978-1-4614-4270-7
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