Abstract
The impact of physical synthesis on design performance is increasing as process technology scales. Current physical synthesis flows generally perform a series of individual netlist transformations based on local timing conditions. However, such optimizations lack sufficient perspective or scope to achieve timing closure in many cases. To address these issues, we develop an integrated transformation system that performs multiple optimizations simultaneously on larger design partitions than existing approaches. Our system, SPIRE, combines physically-aware register retiming, along with a novel form of logic cloning and register placement. SPIRE also incorporates a placement-dependent static timing analyzer (STA) with a delay model that accounts for buffering and is suitable for physical synthesis.
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Notes
- 1.
Indicators are supported by the commercial MILP engine CPLEX 12.1.
- 2.
The Logic-OR can be implemented using intermediary variables \(\delta _A\), \(\delta _B\) and indicator variables \(I_A\), \(I_B\) with the following constraints: \(\delta _A=C-A, \ \ \delta _B=C-B \), \(\ \ I_A \le \delta _A,\ \ \text{ if}(I\_A ==0) \ \delta _A=0\), \( I_b \le \delta _B, \ 6) \ \text{ if}(I_B==0)\ \delta _B=0, I_A + I_B \le 1\).
References
Alpert CJ, Chu C, Villarrubia PG (2007) The coming of age of physical synthesis. ICCAD 2007, pp 246–249
Trevillyan L et al (2004) An integrated environment for technology closure of deep-submicron IC designs. IEEE Des Test Comput 21(1):14–22
Leiserson CE, Saxe JB (1991) “Retiming synchronous circuitry,". Algorithmica 6:5–35
Nair R, Berman C, Hauge P, Yoffa E (1989) Generation of performance constraints for Layout. TCAD 8(8):860–874
Sapatnekar S (2004) Timing. Springer, New York
Sapatnekar SS, Deokar RB (1996) “Utilizing the retiming skew equivalence in a practical algorithm for retiming large circuits,". TCAD 15(10):1237–1248
Zhou H (2009) Deriving a new efficient algorithm for min-period retiming. ASP-DAC 2009, pp 990–993
Hu Y et al (2006) Simultaneous time slack budgeting and retiming for dual-vdd FPGA power reduction. DAC 2006, pp 478–483
Saxena P, Halpin B (2004) Modeling repeaters explicitly within analytical placement. DAC 2004, pp 699–704
Papa DA, Luo T, Moffitt MD, Sze CN, Li Z, Nam G-J, Alpert CJ, Markov IL (2008) RUMBLE: an incremental, timing-driven, physical-synthesis optimization algorithm. IEEE Trans on CAD 27(12):2156–2168
Alpert CJ et al (2007) Techniques for fast physical synthesis. In Proceedings of the IEEE, March 2007, Vol 95, No. 3, pp 573–599
Jess JAG et al (2006) Statistical timing for parametric yield prediction of digital integrated circuits. IEEE Trans on CAD 25(11):2376–2392
Moffitt MD et al (2008) Path smoothing via discrete optimization. DAC 2008, pp 724–727
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Papa, D.A., Markov, I.L. (2013). Logic Restructuring as an Aid to Physical Retiming. In: Multi-Objective Optimization in Physical Synthesis of Integrated Circuits. Lecture Notes in Electrical Engineering, vol 166. Springer, New York, NY. https://doi.org/10.1007/978-1-4614-1356-1_7
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DOI: https://doi.org/10.1007/978-1-4614-1356-1_7
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