Abstract
Modern physical synthesis flows operate on very large designs and perform increasingly aggressive timing optimizations. Traditional incremental timing analysis now represents the single greatest bottleneck in such optimizations and is lacking in features necessary to support them efficiently. We describe a paradigm of transactional timing analysis, which, in addition to incremental updates, offers an efficient, nested undo functionality that does not require significant timing calculations. This paradigm extends traditional incremental Static timing analysis (STA) and enables necessary infrastructure for multiple physical synthesis optimizations in this book.
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Notes
- 1.
Some static timing engines—such as IBM’s EinsTimer\(^{TM}\)—provide similar level-limiting features that serve to circumscribe the scope of local changes; they are not, however, integrated with any form of transaction management.
References
Trevillyan L et al (2004) An integrated environment for technology closure of deep-submicron IC designs. IEEE Design Test Comput 21(1):14–22
Moffitt MD et al (2008) Path smoothing via discrete optimization. DAC 2008, pp 724–727
Kannan LN, Suaris PR, Fang H-G (1994) A methodology and algorithms for post-placement delay optimization. DAC 1994, pp 327–332
Ren H, Pan DZ, Kung DS (2005) Sensitivity guided net weighting for placement-driven synthesis. IEEE Trans CAD 24(5):711–721
Papa DA et al (2008) RUMBLE: an incremental, timing-driven. Physical-synthesis optimization algorithm. ISPD 2008, pp 2–9
Ren H et al (2007) Hippocrates: first-do-no-harm detailed placement. ASP-DAC 2007, pp 141–146.
Chang K-H, Markov IL, Bertacco V (2007) Safe delay optimization for physical synthesis. ASP-DAC 2007, pp 628–633
Drumm AD, Itskin RC, Todd KW (1991) US Patent 5,003,487: method and apparatus for performing timing correction transformations on a technology-independent logic model during logic synthesis, 1991
Abato RP, Drumm AD, Hathaway DJ, van Ginneken LPPP (1996) US Patent 5,508,937: incremental timing analysis, 1996
Lee J-F, Tang DT (1995) An algorithm for incremental timing analysis. DAC 1995, pp 696–701
Sapatnekar SS (1996) Efficient calculation of all-pairs input-to-output delays in synchronous sequential circuits. ISCAS 1996, pp 724–727
Mondal A, Chakrabarti PP, Mandal CR (2004) A new approach to timing analysis using event propagation and temporal logic. DATE 2004, pp 1198–1203
Singh DP, Manohararajah V, Brown SD (2005) Incremental retiming for FPGA physical synthesis. DAC 2005, pp 433–438
Eguro K, Hauck S (2008) Enhancing timing-driven FPGA placement for pipelined netlists. DAC 2008, pp 34–37
Das D et al (2006) FA-STAC: a framework for fast and accurate static timing analysis with coupling. ICCD 2006
Kazda MA et al (2008) US Patent application 20080209376: system and method for sign-off timing closure of a VLSI chip, 2008
Sapatnekar SS (2004) Timing. Kluwer Academic Publishers, Boston
Goering R (2005) Timing analysis needs overhaul. Speaker says. EE Times (February, 2005)
Bronnenberg D (1999) Static timing analysis increases ASIC performance. Integr Sys Design
Wang ARR (1989) Algorithms for multilevel logic optimization. PhD thesis, University of California, 1989
Scheffer L, Lavagno L, Martin G (2006) EDA for IC implementation, circuit design, and process technology. CRC Press, Boca Raton
Mains RE et al (1994) Timing verification and optimization for the power PC processor family. ICCD 1994, pp 390–393
Burstein M, Youssef MN (1985) Timing influenced layout design. DAC 1985, pp 124–130
Donath WE, Kudva P, Stok L, Villarrubia P, Reddy LN, Sullivan A, Chakraborty K (2000) Transformational placement and synthesis. DATE 2000, pp 194–201
Vygen J (2006) Slack in static timing analysis. IEEE Trans CAD 25(9):1876–1885
Donath WE, Hathaway DJ (2001) US Patent 6,202,192: distributed static timing analysis, 2001
Donath WE, Hathaway DJ () US Patent 6,557,151: distributed static timing analysis, 2003
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Papa, D.A., Markov, I.L. (2013). Bounded Transactional Timing Analysis. In: Multi-Objective Optimization in Physical Synthesis of Integrated Circuits. Lecture Notes in Electrical Engineering, vol 166. Springer, New York, NY. https://doi.org/10.1007/978-1-4614-1356-1_4
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DOI: https://doi.org/10.1007/978-1-4614-1356-1_4
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