Bounded Transactional Timing Analysis

  • David A. Papa
  • Igor L. Markov
Part of the Lecture Notes in Electrical Engineering book series (LNEE, volume 166)


Modern physical synthesis flows operate on very large designs and perform increasingly aggressive timing optimizations. Traditional incremental timing analysis now represents the single greatest bottleneck in such optimizations and is lacking in features necessary to support them efficiently. We describe a paradigm of transactional timing analysis, which, in addition to incremental updates, offers an efficient, nested undo functionality that does not require significant timing calculations. This paradigm extends traditional incremental Static timing analysis (STA) and enables necessary infrastructure for multiple physical synthesis optimizations in this book.


Timing Analysis Timing Query Timing Graph Delay Change Lazy Evaluation 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


  1. 1.
    Trevillyan L et al (2004) An integrated environment for technology closure of deep-submicron IC designs. IEEE Design Test Comput 21(1):14–22CrossRefGoogle Scholar
  2. 2.
    Moffitt MD et al (2008) Path smoothing via discrete optimization. DAC 2008, pp 724–727Google Scholar
  3. 3.
    Kannan LN, Suaris PR, Fang H-G (1994) A methodology and algorithms for post-placement delay optimization. DAC 1994, pp 327–332Google Scholar
  4. 4.
    Ren H, Pan DZ, Kung DS (2005) Sensitivity guided net weighting for placement-driven synthesis. IEEE Trans CAD 24(5):711–721Google Scholar
  5. 5.
    Papa DA et al (2008) RUMBLE: an incremental, timing-driven. Physical-synthesis optimization algorithm. ISPD 2008, pp 2–9Google Scholar
  6. 6.
    Ren H et al (2007) Hippocrates: first-do-no-harm detailed placement. ASP-DAC 2007, pp 141–146.Google Scholar
  7. 7.
    Chang K-H, Markov IL, Bertacco V (2007) Safe delay optimization for physical synthesis. ASP-DAC 2007, pp 628–633Google Scholar
  8. 8.
    Drumm AD, Itskin RC, Todd KW (1991) US Patent 5,003,487: method and apparatus for performing timing correction transformations on a technology-independent logic model during logic synthesis, 1991Google Scholar
  9. 9.
    Abato RP, Drumm AD, Hathaway DJ, van Ginneken LPPP (1996) US Patent 5,508,937: incremental timing analysis, 1996Google Scholar
  10. 10.
    Lee J-F, Tang DT (1995) An algorithm for incremental timing analysis. DAC 1995, pp 696–701Google Scholar
  11. 11.
    Sapatnekar SS (1996) Efficient calculation of all-pairs input-to-output delays in synchronous sequential circuits. ISCAS 1996, pp 724–727Google Scholar
  12. 12.
    Mondal A, Chakrabarti PP, Mandal CR (2004) A new approach to timing analysis using event propagation and temporal logic. DATE 2004, pp 1198–1203Google Scholar
  13. 13.
    Singh DP, Manohararajah V, Brown SD (2005) Incremental retiming for FPGA physical synthesis. DAC 2005, pp 433–438Google Scholar
  14. 14.
    Eguro K, Hauck S (2008) Enhancing timing-driven FPGA placement for pipelined netlists. DAC 2008, pp 34–37Google Scholar
  15. 15.
    Das D et al (2006) FA-STAC: a framework for fast and accurate static timing analysis with coupling. ICCD 2006Google Scholar
  16. 16.
    Kazda MA et al (2008) US Patent application 20080209376: system and method for sign-off timing closure of a VLSI chip, 2008Google Scholar
  17. 17.
    Sapatnekar SS (2004) Timing. Kluwer Academic Publishers, BostonMATHGoogle Scholar
  18. 18.
    Goering R (2005) Timing analysis needs overhaul. Speaker says. EE Times (February, 2005)Google Scholar
  19. 19.
    Bronnenberg D (1999) Static timing analysis increases ASIC performance. Integr Sys DesignGoogle Scholar
  20. 20.
    Wang ARR (1989) Algorithms for multilevel logic optimization. PhD thesis, University of California, 1989Google Scholar
  21. 21.
    Scheffer L, Lavagno L, Martin G (2006) EDA for IC implementation, circuit design, and process technology. CRC Press, Boca RatonGoogle Scholar
  22. 22.
    Mains RE et al (1994) Timing verification and optimization for the power PC processor family. ICCD 1994, pp 390–393Google Scholar
  23. 23.
    Burstein M, Youssef MN (1985) Timing influenced layout design. DAC 1985, pp 124–130Google Scholar
  24. 24.
    Donath WE, Kudva P, Stok L, Villarrubia P, Reddy LN, Sullivan A, Chakraborty K (2000) Transformational placement and synthesis. DATE 2000, pp 194–201Google Scholar
  25. 25.
    Vygen J (2006) Slack in static timing analysis. IEEE Trans CAD 25(9):1876–1885Google Scholar
  26. 26.
    Donath WE, Hathaway DJ (2001) US Patent 6,202,192: distributed static timing analysis, 2001Google Scholar
  27. 27.
    Donath WE, Hathaway DJ () US Patent 6,557,151: distributed static timing analysis, 2003Google Scholar

Copyright information

© Springer Science+Business Media New York 2013

Authors and Affiliations

  • David A. Papa
    • 1
  • Igor L. Markov
    • 2
  1. 1.Broadway TechnologyAustinUSA
  2. 2.University of MichiganAnn ArborUSA

Personalised recommendations