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Methodology in Computer-Aided Design for Process and Device Development

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Computer-Aided Design and VLSI Device Development

Abstract

The previous chapters have presented an overview of computer-aided design (CAD) in VLSI development, as well as the simulation tools currently used at Hewlett-Packard Laboratories. In this chapter, CAD is discussed from the user point of view. The methodology for using the simulation tools in the most effective way is presented. Then case studies will be presented in the following chapters which show in detail how simulation tools are used in device designs.

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References

  1. K. M. Cham and S. Y. Chiang, “Device Design for the Submicrometer P-Channel FET with n+ Polysilicon Gate,” IEEE Trans. on Electron Devices, ED-31, July 1984, pp. 964–968.

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  3. S. M. Sze, Physics of Semiconductor Devices, 2 nd ed., NY:Wiley Inter-science, 1981.

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  4. R. R. Troutman, “VLSI Limitations from Drain-Induced Barrier Lowering,” Trans. on Electron Devices, ED-27, April 1979, pp. 461–468.

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© 1988 Kluwer Academic Publishers, Boston

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Cham, K.M., Oh, SY., Moll, J.L., Lee, K., Vande Voorde, P., Chin, D. (1988). Methodology in Computer-Aided Design for Process and Device Development. In: Computer-Aided Design and VLSI Device Development. The Kluwer International Series in Engineering and Computer Science, vol 53. Springer, Boston, MA. https://doi.org/10.1007/978-1-4613-1695-4_6

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  • DOI: https://doi.org/10.1007/978-1-4613-1695-4_6

  • Publisher Name: Springer, Boston, MA

  • Print ISBN: 978-1-4612-8956-2

  • Online ISBN: 978-1-4613-1695-4

  • eBook Packages: Springer Book Archive

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