Computer-Aided Design and VLSI Device Development

1. Front Matter

   Pages i-xiii

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2. Overview

   1. Overview

      • Kit Man Cham, Soo-Young Oh, John L. Moll, Keunmyung Lee, Paul Vande Voorde, Daeje Chin

      Pages 1-10

3. Numerical Simulation Systems

   1. Front Matter

      Pages 11-11

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   2. Numerical Simulation Systems

      • Kit Man Cham, Soo-Young Oh, John L. Moll, Keunmyung Lee, Paul Vande Voorde, Daeje Chin

      Pages 13-21

   3. Process Simulation

      • Kit Man Cham, Soo-Young Oh, John L. Moll, Keunmyung Lee, Paul Vande Voorde, Daeje Chin

      Pages 23-69

   4. Device Simulation

      • Kit Man Cham, Soo-Young Oh, John L. Moll, Keunmyung Lee, Paul Vande Voorde, Daeje Chin

      Pages 71-127

   5. Parasitic Elements Simulation

      • Kit Man Cham, Soo-Young Oh, John L. Moll, Keunmyung Lee, Paul Vande Voorde, Daeje Chin

      Pages 129-140

4. Applications and Case Studies

   1. Front Matter

      Pages 141-141

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   2. Methodology in Computer-Aided Design for Process and Device Development

      • Kit Man Cham, Soo-Young Oh, John L. Moll, Keunmyung Lee, Paul Vande Voorde, Daeje Chin

      Pages 143-150

   3. SUPREM III Application

      • Kit Man Cham, Soo-Young Oh, John L. Moll, Keunmyung Lee, Paul Vande Voorde, Daeje Chin

      Pages 151-165

   4. Simulation Techniques for Advanced Device Development

      • Kit Man Cham, Soo-Young Oh, John L. Moll, Keunmyung Lee, Paul Vande Voorde, Daeje Chin

      Pages 167-195

   5. Drain-Induced Barrier Lowering in Short Channel Transistors

      • Kit Man Cham, Soo-Young Oh, John L. Moll, Keunmyung Lee, Paul Vande Voorde, Daeje Chin

      Pages 197-209

   6. A Study of LDD Device Structure Using 2-D Simulations

      • Kit Man Cham, Soo-Young Oh, John L. Moll, Keunmyung Lee, Paul Vande Voorde, Daeje Chin

      Pages 211-231

   7. The Surface Inversion Problem in Trench Isolated CMOS

      • Kit Man Cham, Soo-Young Oh, John L. Moll, Keunmyung Lee, Paul Vande Voorde, Daeje Chin

      Pages 233-250

   8. Development of Isolation Structures for Applications in VLSI

      • Kit Man Cham, Soo-Young Oh, John L. Moll, Keunmyung Lee, Paul Vande Voorde, Daeje Chin

      Pages 251-270

   9. Transistor Design for Submicron CMOS Technology

      • Kit Man Cham, Soo-Young Oh, John L. Moll, Keunmyung Lee, Paul Vande Voorde, Daeje Chin

      Pages 271-300

   10. A Systematic Study of Transistor Design Traae-offs

       • Kit Man Cham, Soo-Young Oh, John L. Moll, Keunmyung Lee, Paul Vande Voorde, Daeje Chin

       Pages 301-313

   11. MOSFET Scaling by CADDET

       • Kit Man Cham, Soo-Young Oh, John L. Moll, Keunmyung Lee, Paul Vande Voorde, Daeje Chin

       Pages 315-334

   12. Examples of Parasitic Elements Simulation

       • Kit Man Cham, Soo-Young Oh, John L. Moll, Keunmyung Lee, Paul Vande Voorde, Daeje Chin

       Pages 335-357

5. Back Matter

   Pages 359-379

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examples are presented. These chapters are intended to introduce the reader to the programs. The program structure and models used will be described only briefly. Since these programs are in the public domain (with the exception of the parasitic simulation programs), the reader is referred to the manuals for more details. In this second edition, the process program SUPREM III has been added to Chapter 2. The device simulation program PISCES has replaced the program SIFCOD in Chapter 3. A three-dimensional parasitics simulator FCAP3 has been added to Chapter 4. It is clear that these programs or other programs with similar capabilities will be indispensible for VLSI/ULSI device developments. Part B of the book presents case studies, where the application of simu­ lation tools to solve VLSI device design problems is described in detail. The physics of the problems are illustrated with the aid of numerical simulations. Solutions to these problems are presented. Issues in state-of-the-art device development such as drain-induced barrier lowering, trench isolation, hot elec­ tron effects, device scaling and interconnect parasitics are discussed. In this second edition, two new chapters are added. Chapter 6 presents the methodol­ ogy and significance of benchmarking simulation programs, in this case the SUPREM III program. Chapter 13 describes a systematic approach to investi­ gate the sensitivity of device characteristics to process variations, as well as the trade-otIs between different device designs.

• CMOS
• MOSFET
• VLSI
• computer
• development
• interconnect
• simulation
• transistor

• Hewlett-Packard Laboratories, UK

  Kit Man Cham, Soo-Young Oh, John L. Moll, Keunmyung Lee, Paul Voorde

• Samsung Semiconductor, UK

  Daeje Chin

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