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Abstract

In this chapter, the design of transistors for submicron CMOS technology will be presented. The advantages of, as well as issues involved in CMOS technology will first be discussed. Then the concerns for the design of n- and p-channel MOSFET’s with submicron channel lengths will be discussed. Using simulations, the values of the critical device parameters are determined which will minimize leakage problems in submicron transistors.

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References

  1. F. Lee, N. Godinho, and C. P. Chiu, “Cool-Running 16K RAM Rivals N-Channel MOS Performance,” Electronics, Oct 6,1981, pp. 120–123.

    Google Scholar 

  2. Y. El-Mansy, “MOS Device and Technology Constraints in VLSI,” IEEE Trans, on Electron Devices, ED-29, Apr 1982, pp. 567–573.

    Article  Google Scholar 

  3. L. C. Thomas and J. J. Molinelli, “VLSI Logic,” Tech Digest of ISSCC 1981, pp. 230–231.

    Google Scholar 

  4. R. R. Troutman, “Recent Developments in CMOS Latchup,” Tech. Digest of IEDM 1984, pp. 296–299.

    Google Scholar 

  5. D. B. Estreich, “The Physics and Modeling of Latch-up in CMOS Integrated Circuits,” Stanford Electronics Labs Report #G-201–9,1980.

    Google Scholar 

  6. S. E. Laux and F. H. Gaensslen, “A Study of Avalanche Breakdown in Scaled N-Channel MOSFET’s,” Tech. Digest of IEDM 1984, pp. 84–86.

    Google Scholar 

  7. C. Hu, “Hot Electron Effects in MOSFET’s,” Tech. Digest of IEDM 1983, pp. 176–181.

    Google Scholar 

  8. K. M. Cham, D. W. Wenocur, J. Lin, C. K. Lau, H.-S. Fu, “Submicrometer Thin Gate Oxide P-Channel Transistors with P+ Polysilicon Gates for VLSI Applications,” IEEE Electron Device Lett., EDL-7, Jan. 1986, pp. 49–52.

    Article  Google Scholar 

  9. S. J. Hillenius, R. Liu, G. E. Georgiou, R. L. Field, D. S. Williams, A. Kornblit, D. M. Boulin, R. L. Johnston, W. T. Lynch, “A Symmetric Submicron CMOS Technology,” Tech. Digest of IEDM 1986, pp. 252–255.

    Google Scholar 

  10. K. M. Cham and S. Y. Chiang, “Device Design for the Submicrometer p-Channel FET with n+ Polysilicon Gate,” IEEE Trans, on Electron Devices, ED-31, July 1984, pp. 964–968.

    Article  Google Scholar 

  11. D. V. Morgan, Ed., Channeling: Theory, Observation and Applications, New York:Wiley, 1973.

    Google Scholar 

  12. T. Kobayashi, S. Horiguchi and K. Kiuchi, “Deep-Submicron MOSFET Characteristics with 5nm Gate Oxide,” Tech. Digest of IEDM 1984, pp. 414–417.

    Google Scholar 

  13. J. R. Brews, W. Fichtner, E. H. Nicollian, and S. M. Sze, “Generalized Guide for MOSFET Miniaturization,” IEEE Electron Devices Lett., EDL-1, Jan 1980, pp. 2–4.

    Article  Google Scholar 

  14. S. Odanaka, M. Fukumoto, G. Fuse, M. Sasago, T. Yabu, and T. Ohzone, “A New Half-Micrometer P-Channel MOSFET with Efficient Punchthrough Stops,” IEEE Trans, on Electron Devices, ED-33, Mar. 1986, pp. 317–321.

    Article  Google Scholar 

  15. E. Takeda, Y. Nakagome, H. Kume, N. Susuki, and S. Asai, “Comparison of Characteristics of n-Channel and p-Channel MOSFET’s for VLSFs,” IEEE Trans. on Electron Devices, ED-30, June 1983, pp. 675–680.

    Article  Google Scholar 

  16. H. Katto, K. Okuyama, S. Megure, R. Nagai and S. Ikeda, “Hot Carrier Degradation Modes and Optimization of LDD MOSFET’s,” Tech. Digest of IEDM 1984, pp. 774–777.

    Google Scholar 

  17. K. Balasubramanyam, M. J. Hargrove, H. I. Hanafi, M. S. Lin, D. Hoy-niak, J. LaRue and D. R. Thomas, “Characterization of As-P Double Diffused Drain Structure,” Tech. Digest of IEDM 1984, pp. 782–785.

    Google Scholar 

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© 1988 Kluwer Academic Publishers, Boston

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Cham, K.M., Oh, SY., Moll, J.L., Lee, K., Vande Voorde, P., Chin, D. (1988). Transistor Design for Submicron CMOS Technology. In: Computer-Aided Design and VLSI Device Development. The Kluwer International Series in Engineering and Computer Science, vol 53. Springer, Boston, MA. https://doi.org/10.1007/978-1-4613-1695-4_13

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  • DOI: https://doi.org/10.1007/978-1-4613-1695-4_13

  • Publisher Name: Springer, Boston, MA

  • Print ISBN: 978-1-4612-8956-2

  • Online ISBN: 978-1-4613-1695-4

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