The Surface Inversion Problem in Trench Isolated CMOS

Abstract

Trench isolation has recently been proposed for advanced CMOS processes [10.1]–[10.4]. Fig. 10.1 shows a trench isolated CMOS structure. The major advantage of trench isolation in CMOS is to reduce the latchup problem [10.5],[10.6]. Fig. 10.2 shows the latchup path for a CMOS structure, where the parasitic bipolar transistors are shown to form a positive feedback path. If there is excess current flow in the n-well and substrate, and if the substrate and n-well resistances are large enough, significant voltage drops will occur in the substrate and n-well. Under this condition, the parasitic bipolar transistors can be turned on [10.5]. This phenomenon has been studied by many researchers in CMOS technology. The trench has been suggested as a good candidate for isolation between n-channel and p-channel transistors. For an n-well process it is expected that the lateral n-p-n parasitic bipolar transistor gain will be reduced, thereby increasing the latchup initiating current. In a p-well process, the reduction of latchup sensitivity is achieved from reduction of the lateral parasitic p-n-p current gain.