Abstract
This chapter reviews the several models which have been developed to predict the yield of monolithic circuits. Circuit faults arise from a variety of effects. Defects during patterning or film depositions can lead to shorts, open lines or defective transistors, as discussed in the previous chapter. Such defect-based faults are considered in this chapter. However, faults also arise through degradation in features, such as electromigration failure of aluminum interconnections, which cause failure of an operational circuit after some period of operation. Such faults are called failures and are addressed under the topic of reliability. Other faults arise from violation of design rules (i.e. placing diffusions too close to one another, insufficient spacing between metal interconnections, etc). Such design rule violations are not considered here under the presumption that CAD-based design rule checkers catch such violations. Another category of faults arises from statistical parameter variations arising during processing. Yield degradation due to such fabrication variations are called parametric yield [1,2,3], resulting in circuits which do not operate within specification. Though of considerable importance in developing a VLSI fabrication line, parametric yield is beyond the scope of this book.
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© 1989 Kluwer Academic Publishers
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Tewksbury, S.K. (1989). Yield Models and Analysis. In: Wafer-Level Integrated Systems. The Kluwer International Series in Engineering and Computer Science, vol 70. Springer, Boston, MA. https://doi.org/10.1007/978-1-4613-1625-1_5
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DOI: https://doi.org/10.1007/978-1-4613-1625-1_5
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