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Wafer-Level Integrated Systems

Implementation Issues

  • Book
  • © 1989

Overview

Authors:
  1. Stuart K. Tewksbury

    1. AT&T Bell Laboratories, USA

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Table of contents (13 chapters)

  1. Front Matter

    Pages i-xv
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  2. Introduction

    • Stuart K. Tewksbury
    Pages 1-22

  3. Interconnect Issues

    • Stuart K. Tewksbury
    Pages 23-73

  4. Fabrication Defects

    • Stuart K. Tewksbury
    Pages 75-114

  5. Reliability and Failures

    • Stuart K. Tewksbury
    Pages 115-146

  6. Yield Models and Analysis

    • Stuart K. Tewksbury
    Pages 147-179

  7. Fault Modeling

    • Stuart K. Tewksbury
    Pages 181-206

  8. General Testing Techniques

    • Stuart K. Tewksbury
    Pages 207-243

  9. Function-Specific Testing

    • Stuart K. Tewksbury
    Pages 245-279

  10. Physical Restructuring

    • Stuart K. Tewksbury
    Pages 281-312

  11. Programmable Electronic Reconfiguration Switches

    • Stuart K. Tewksbury
    Pages 313-349

  12. Formal Models of Reconfiguration

    • Stuart K. Tewksbury
    Pages 351-385

  13. Silicon Wafer Hybrids

    • Stuart K. Tewksbury
    Pages 387-417

  14. Optical Interconnections

    • Stuart K. Tewksbury
    Pages 419-450

  15. Back Matter

    Pages 451-456
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Keywords

About this book

From the perspective of complex systems, conventional Ie's can be regarded as "discrete" devices interconnected according to system design objectives imposed at the circuit board level and higher levels in the system implementation hierarchy. However, silicon monolithic circuits have progressed to such complex functions that a transition from a philosophy of integrated circuits (Ie's) to one of integrated sys­ tems is necessary. Wafer-scale integration has played an important role over the past few years in highlighting the system level issues which will most significantly impact the implementation of complex monolithic systems and system components. Rather than being a revolutionary approach, wafer-scale integration will evolve naturally from VLSI as defect avoidance, fault tolerance and testing are introduced into VLSI circuits. Successful introduction of defect avoidance, for example, relaxes limits imposed by yield and cost on Ie dimensions, allowing the monolithic circuit's area to be chosen according to the natural partitioning of a system into individual functions rather than imposing area limits due to defect densities. The term "wafer­ level" is perhaps more appropriate than "wafer-scale". A "wafer-level" monolithic system component may have dimensions ranging from conventional yield-limited Ie dimensions to full wafer dimensions. In this sense, "wafer-scale" merely represents the obvious upper practical limit imposed by wafer sizes on the area of monolithic circuits. The transition to monolithic, wafer-level integrated systems will require a mapping of the full range of system design issues onto the design of monolithic circuit.

Authors and Affiliations

  • AT&T Bell Laboratories, USA

    Stuart K. Tewksbury

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