Wafer-Level Integrated Systems pp 351-385 | Cite as

# Formal Models of Reconfiguration

## Abstract

This section reviews several of the fundamental results on the “reconfigurability” of linear or 2-dimensional arrays of *N* cells as *N* becomes large. Details of the actual reconfiguration mechanisms (i.e. switches and redundant interconnection lines) are not emphasized, since the principal objective here is to obtain general bounds which can be used to clarify constraints which necessarily apply to specific reconfiguration schemes. Greene and Gamal [1] developed several probabilistic bounds on array reconfiguration and their early study stimulated considerable subsequent work on this topic. Leighton and Leiserson [2] provide a review of algorithms for WSI systolic array reconfiguration, emphasizing large *N* and the probabilistic bounds on “wire length.” Unbounded increases in wire length would impose a particularly severe constraint on systolic array reconfiguration since the rate of data flow movement through the array becomes limited by the longest delay path. For example, the uniform length, nearest neighbor interconnections of an ideal systolic array provide much of the impetus for systolic array designs in the first place. Introduction of reconfiguration schemes, which introduce interconnections of varying length, destroys the homogeneity of interconnection lengths of the ideal systolic arrays. In addition to this obvious reason to minimize the worst case interconnection length (in pipelined, high throughput rate systolic arrays), there is also an expected increase in the number of reconfiguration wires bypassing each cell as the reconfiguration path distances increase.

### Keywords

Hexagonal Expense Pyramid Percolate Lori## Preview

Unable to display preview. Download preview PDF.

### References

- [1]J. W. Greene and A. El Gainai,
*Configuration of VLSI arrays in the presence of defects*, J. ACM, vol. 31, pp. 694–717 (1984).MATHCrossRefGoogle Scholar - [2]T. Leighton and C. E. Leiserson,
*Wafer-scale integration of systolic arrays*, IEEE Trans. Computers, vol. C-34, pp. 448–461 (1985).CrossRefGoogle Scholar - [3]R. M. Lea,
*A WSI image processing module*, in*Wafer Scale Integration*, G. Saucier and J. Trihle (Eds), Elsevier Science Pubs., pp. 43–58 (1986).Google Scholar - [4]R. M. Lea,
*VLSI and WSI associative string processors for structured data processing*, IEE Proc., vol. 133 (Pt.E), pp. 153–162 (1986).Google Scholar - [5]R. M. Lea,
*VLSI and WSI associative string processors for cost-effective parallel processing*, The Computer Journal, vol. 29, pp. 486–494 (1986).CrossRefGoogle Scholar - [6]W. R. Moore and M. J. Day,
*Yield enhancement of a large systolic array chip*, Microelectron. Reliab., vol. 24, pp. 511–526 (1984).CrossRefGoogle Scholar - [7]T. Leighton and C. E. Leiserson,
*A survey of algorithms for integrating waferscale systolic arrays*, Tech. Report MIT/LCS/TM-302, Laboratory for Comp. Sci., MIT (1986).Google Scholar - [8]A. Aho, J. E. Hopcroft and J. D. Ullman,
*Data Structures and Algorithms*, pp. 233–239, Addison-Wesley Publ. Co., Reading MA (1983).MATHGoogle Scholar - [9]M. Sekanina,
*On the ordering of the set of vertices of a connected graph*, Pub. Faculty of Sci., Univ. Brno, Czechoslovakia, no. 412, pp. 137–142 (1960).MathSciNetGoogle Scholar - [10]J. J. Karaganis,
*On the cube of a graph*, Canad. Math Bull., no. 11, pp. 295–296 (1968).Google Scholar - [11]J. C. Wierman,
*Percolation theory*, Ann. Prob., vol. 10, pp. 509–524 (1982).MathSciNetMATHCrossRefGoogle Scholar - [12]M. S. Lee and G. Frieder,
*Computations on a defective processor array*, Proc. IEEE CompEuro, pp. 51–55 (1987).Google Scholar - [13]H. Frisch, J. M. Hammersley and D. J. A. Welsh,
*Monte Carlo estimates of percolation probabilities for various lattices*, Phys. Rev., vol. 126, pp. 949–951 (1962).CrossRefGoogle Scholar - [14]M. F. Sykes and J. W. Essam,
*Exact critical percolation probabilities for site and bond problems in two dimensions*, J. Math. Phys., vol. 5, pp. 1117–1127 (1964).MathSciNetCrossRefGoogle Scholar - [15]C. D. Thompson,
*A complexity theory for VLSI*, Ph.D. Thesis, Dept. of Computer Science, Carnegie-Mellon University, pp. 36–38 (1980).Google Scholar - [16]A. L. Rosenberg,
*The Diogenes approach to testable fault-tolerant arrays of processors*, IEEE Trans. Computers, vol. C-32, pp. 902–910 (1983).CrossRefGoogle Scholar - [17]A. L. Rosenberg,
*On designing fault-tolerant VLSI processor arrays*, in*Advances in Computing Research*,, F. P. Preparata (Ed), vol. 2, pp. 181–204 (1984).Google Scholar - [18]A. L. Rosenberg,
*A hypergraph model for fault-tolerant VLSI processor arrays*, IEEE Trans. Computers, vol. C-34, pp. 578–584 (1985).CrossRefGoogle Scholar - [19]A. L. Rosenberg
*Graph-theoretic approaches to fault-tolerant WSI*, in*Wafer Scale Integration*, C. Jesshope and W. Moore (Eds), pp. 10–23, Adam Hilger (1986).Google Scholar - [20]A. L. Rosenberg
*Fault-tolerant WSI processor arrays*, Technical Report, Dept. of Computer Science, Duke University (Sept. 1987).Google Scholar - [21]R. Negrini and R. Stefanelli,
*Comparative evaluation of space- and time- redundancy approaches for WSI processing arrays*, in*Wafer Scaie Integration*, G. Saucier and J. Trihle (eds), Elsevier Science Pubs., pp. 207–222 (1986).Google Scholar - [22]R. Negrini, M. G. Sami and R. Stefanelli,
*Fault-tolerance approaches for VLSI/WSI arrays*, Proc. IEEE Int. Phoenix Conf. on Computers and Commun., pp. 460–468 (1985).Google Scholar - [23]G. Gentile, M. G. Sami and M. Terzoli,
*Design of switches for selfreconfiguring VLSI array structures*, Microprocessing and Microprogramming, vol. 14, pp. 99–108 (1984).CrossRefGoogle Scholar - [24]V. N. Doniants, S. Iori, M. Pellegrino, E. I. Pi’il and R. Stefanelli,
*Faulttolerant reconfigurable processing arrays using bi-directional switches*, Microprocessing and Microprogramming, vol. 14, pp. 109–115 (1984).CrossRefGoogle Scholar - [25]V. N. Donaints, V. G. Lazarev, M. G. Sami and R. Stefanelli,
*Reconfiguration of VLSI arrays: a technique for increased flexibility and reliability*, Microprocessing and Microprogramming, vol. 16, pp. 101–106 (1985)CrossRefGoogle Scholar - [26]A. Antola, R. Negrini and N. Scarabottolo,
*An approach to fault-tolerance in architectures for discrete Fourier transforms*, Microprocessing and Microprogramming, vol. 18, pp. 275–288 (1986).CrossRefGoogle Scholar - [27]R. Negrini, M. Sami and R. Stefanelli,
*Fault tolerance techniques for array structures used in supercomputing*, IEEE Computer, pp. 78–87 (Feb 1986).Google Scholar - [28]F. Lombardi, M. G. Sami and R. Stefanelli,
*Reconfiguration of VLSI arrays: an index mapping approach*, Proc. IEEE CompEuro, pp. 60–65 (1987).Google Scholar - [29]F. Lombardi, D. Sciuto and R. Stefanelli,
*Functional reconfiguration in fixedsize VLSI arrays*, Proc. IEEE Int. Symp. Circuits and Systems, pp. 386–389 (1987).Google Scholar - [30]C.-L. Wey and F. Lombardi,
*On the repair of redundant RAM’s*, IEEE Trans. Comp. Aided Design, vol. CAD-6, pp. 222–231 (1987).Google Scholar - [31]F. Lombardi and D. Sciuto,
*Algorithms for delay-bound reconfiguration of arrays*, in*Wafer Scale Integration*, G. Saucier and J. Tritile (Eds), pp. 197–206 (1986).Google Scholar - [32]J. A. B. Fortes and C. S. Raghavendra,
*Gracefully degradable processor arrays*, IEEE Trans. Computers, vol. C-34, pp. 1033–1044 (1985).CrossRefGoogle Scholar - [33]S.-Y. Kuo and W. K. Fuchs,
*Efficient spare allocation for reconfigurable arrays*, IEEE Design and Test, pp. 24–31 (Jan 1987).Google Scholar - [34]M. Tarr, D. Boudreau and R. Murphy,
*Defect analysis speeds test and repair of redundant memories*, Electronics, pp. 175–179, (Jan 12, 1984).Google Scholar - [35]J. D. Day, A fault-driven comprehensive redundancy algorithm, IEEE Design and Test, vol. 2, pp. 35–44 (June 1985).CrossRefGoogle Scholar