Wafer-Level Integrated Systems pp 351-385 | Cite as

# Formal Models of Reconfiguration

## Abstract

This section reviews several of the fundamental results on the “reconfigurability” of linear or 2-dimensional arrays of *N* cells as *N* becomes large. Details of the actual reconfiguration mechanisms (i.e. switches and redundant interconnection lines) are not emphasized, since the principal objective here is to obtain general bounds which can be used to clarify constraints which necessarily apply to specific reconfiguration schemes. Greene and Gamal [1] developed several probabilistic bounds on array reconfiguration and their early study stimulated considerable subsequent work on this topic. Leighton and Leiserson [2] provide a review of algorithms for WSI systolic array reconfiguration, emphasizing large *N* and the probabilistic bounds on “wire length.” Unbounded increases in wire length would impose a particularly severe constraint on systolic array reconfiguration since the rate of data flow movement through the array becomes limited by the longest delay path. For example, the uniform length, nearest neighbor interconnections of an ideal systolic array provide much of the impetus for systolic array designs in the first place. Introduction of reconfiguration schemes, which introduce interconnections of varying length, destroys the homogeneity of interconnection lengths of the ideal systolic arrays. In addition to this obvious reason to minimize the worst case interconnection length (in pipelined, high throughput rate systolic arrays), there is also an expected increase in the number of reconfiguration wires bypassing each cell as the reconfiguration path distances increase.

## Keywords

Span Tree Bipartite Graph Linear Array Systolic Array Functional Cell## Preview

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