Abstract
Although physical reconfiguration/restructuring switches dominate most commercial reconfigured VLSI circuits (e.g. memory repair), electronic switches are prominently used in experimental logic circuits designed for yield enhancement. Figure 10.1 shows the general model of an electronic switch for reconfiguration of interconnections. In addition to the specific switching of an input line INPUT to an output line OUTPUT, the open/closed state of the switch must be stored at the switch site. Furthermore, since the programmable electronic switches considered here are often volatile, that open/closed state information may have to be externally loaded into the storage node (typically a flip-flop or a latch). In Figure 10.1, this external loading is provided by two global lines, one providing the switch state and the other a control signal loading that state into the storage node.
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References
R. M. Lea, A WSI image processing module, in Wafer Scaie Integration, G. Saucier and J. Trihle (Eds), Elsevier Science Pubs., Amsterdam, The Netherlands, pp. 43–58 (1986).
D. L. Carter and D. F. Guise, Effects of interconnects on submicron chip performance, VLSI Design, pp. 63–68 (1984).
H. B. Bakoglu and J. D. Meindl, Optimal interconnection circuits for VLSI, IEEE Trans. Electron Devices, vol. ED-32, pp. 903–909 (1985).
R. Negrini and R. Stefanelli, Comparative evaluation of space- and time- redundancy approaches for WSI associative processors, in Wafer Scaie Integration, G. Saucier and J. Trihle (Eds), Elsevier Science Pubs., Amsterdam, The Netherlands, pp. 207–222 (1986).
L. Snyder, Overview of the CHiP computer, in VLSI 81, John P. Gray (ed), pp. 237–246, Academic Press (1981).
L. Snyder, Introduction to the configurable highly parallel computer, IEEE Computer, vol. 15, pp. 47–56 (1982).
K. S. Hedlund, Wafer scale integration of parallel processors, Ph.D. Thesis, Comp. Science Dept., Purdue Univ. (Dec. 1982).
K. S. Hedlund and L. Snyder, Wafer scale integration of configurable highly parallel (CHiP) processors, Proc. IEEE Int. Conf. on Parallel Proc. pp. 262–264 (1982).
K. S. Hedlund and L. Snyder, Systolic architecture — a wafer scale approach, Proc. IEEE Int Conf. Comp. Design, pp. 604–610 (1984).
K. S. Hedlund, WASP — a WAfer-scale Systolic Processor, Proc. IEEE Int. Conf. Comp. Design, pp. 665–671 (1985).
S. Yalamanchili and J. K. Aggarwal, Reconfigurable strategies for parallel architectures, IEEE Computer, vol. 18, pp. 44–61 (1985)
L. Snyder, Programming processor interconnection structures, Tech. Report CDS-TR-381, Dept. of Computer Science, Purdue University (Oct. 1981).
L. Snyder, Overview of the CHiP computer, Tech. Report CDS-TR-377, Dept. of Computer Science, Purdue University (Aug 19, 1981).
J. T. Field, A. A. Kapauan and L. Snyder, Pringle: a parallel processor to emulate CHiP computers, Tech. Report CSD-TR-433, Dept. of Computer Science, Purdue University (Jan. 1983).
C.-C. Hsiao, Highly parallel processing of relational databases, Tech. Report CSD-TR-460, Dept. of Computer Science, Purdue University (Aug. 1983).
L. Snyder, Parallel programming and the poker programming environment, IEEE Computer, pp. 27–36 (1984).
K. S. Hedlund, The design of a prototype WASP machine, in Wafer Scale Integration, Saucier and Trihle (eds), Elsevier Science Pubs., Amsterdam, The Netherlands, pp. 89–97 (1986).
C. Mead and L. Conway, Introduction to VLSI systems, Addison-Wesley, Reading, MA (1980).
Y.-H. Choi, D. S. Fussell and M. Malek, Fault diagnosis of switches in waferscale arrays, Proc. IEEE Int. Conf. Computer-Aided Design, pp. 292–295 (1986).
M.G.H. Katevenis and M. G. Blatt, Switch design for soft-configurable WSI systems, in Wafer Scaie Integration, G. Saucier and J. Trihle (Eds), Elsevier Science Pub., Amsterdam, The Netherlands, pp. 255–270, (1986).
P. Franzon and S. K. Tewksbury, Chip-frame scheme for reconfigurable mesh connected arrays, IFIP Workshop on Wafer Scale Integration, Brunei University, Sept. 23–25 (1987).
S. K. Tewksbury and L. A. Hornak, Future physical environments and concurrent computations, in Concurrent Computations: Algorithms, Architecture and Technology, S. K. Tewksbury, B. Dickinson and S. Schwartz (Eds), Plenum Press (1988).
V. N. Doniants, V. G. Lazarev, M. G. Sami and R. Stefanelli, Reconfiguration of VLSI arrays: a technique for increased flexibility and reliability, Microprocessing and Microprogramming, vol. 16, pp. 101–106 (1985).
G. Chevalier and G. Saucier, A programmable switch matrix for the wafer scale integration of a processor array, in Wafer Scaie Integration, C. Jesshope and W. Moore (Eds), Adam Hilger, pp. 92–100 (1986).
R. Schuck and M. Glessner, A WSI system for the computation of the two dimensional Fast Fourier Transform, in Wafer Scaie Integration, C. Jesshope and W. Moore (eds), Adam Hilger Pub., pp. 179–186 (1986).
J. Beichter and U. Ramacher, A self-testing WSI matrix multiplier, IFIP Workshop on Wafer Scale Integration, Sept. 23–24, Brunei Univ. (1987).
S.-Y. Rung, K. S. Arun, R. J. Galezer and D. K. B. Rao, Wavefront array processor: language, architecture and applications, IEEE Trans. Comp, vol. C-31, pp. 1054–1066 (1982).
V. N. Doniants, S. Iori, M. Pelligrino, E. I. Pi’il and R. Stefanelli, Faulttolerant reconfigurable processing arrays using bi-directional switches, Microprocessing and Microprogramming, vol. 14, pp. 109–115 (1984).
W. Chen, P. B. Denyer, J. Mavor and D. Renshaw, Fault-tolerant wafer scale architectures using large crossbar switch arrays, in Wafer Scaie Integration, C. Jesshope and W. Moore (eds), Adam Hilger, pp. 113–124 (1986).
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© 1989 Kluwer Academic Publishers
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Tewksbury, S.K. (1989). Programmable Electronic Reconfiguration Switches. In: Wafer-Level Integrated Systems. The Kluwer International Series in Engineering and Computer Science, vol 70. Springer, Boston, MA. https://doi.org/10.1007/978-1-4613-1625-1_10
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DOI: https://doi.org/10.1007/978-1-4613-1625-1_10
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