Abstract
Before the introduction, it is necessary to differentiate power and energy first, especially for battery operated system. Power is the instantaneous power dissipation in the system, and energy is the integral of power over time. The power used by a given system varies over time depending on what it is doing, while it is energy that determines battery life.
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References
Michael Keating, David Flynn, Robert Aitken, et al. Low Power Methodology Manual: For SoC Design[M]. New York: Springer, 2007.
Jan Rabacy. Low Power Design Essentials[M]. New York: Springer, 2009.
Jan M. Rabacy, Anantha Chandrakasan, Borivoje Nikolic. Digital Integrated Circuits: A Design Perspective (Second Edition) [M]. Beijing: Tsinghua, 2004.
Hao Dongyan, Zhang Ming, Zheng Wei. Design Methodology of CMOS Low Power. IEEE, 2005.
Bo Zhang, Liping Liang, Xingjun Wang. A New Level Shifter with Low Power in Multi-Voltage System. IEEE, 2006.
Stephanie Ann Augsburger. Using Dual-Supply, Dual-Threshold and Transistor Sizing to Reduce Power in Digital Integrated Circuits[M. S. thesis]. Berkeley, The USA: University of California at Berkeley. 2002.
Danny P. Riemens. Exploring suitable adder designs for biomedical implants[M. S. thesis]. Delft, The Netherlands: Delft University of Technology. 2010.
Chris H. Kim and Kaushik Roy. Dynamic VTH scaling scheme for active leakage power reduction [C]. Proceedings of the 2002 Design, Automation and Test in Europe Conference and Exhibition (DATE.02), 2002.
David Duarte, Yuh-Fang Tsai, Narayanan Vijaykrishnan, et al. Evaluating Run-Time Techniques for Leakage Power Reduction[C]. Proceedings of the 15th International Conference on VLSI Design (VLSID.02), Bangalore, India, 2002.
A. Correale, Overview of the Power Minimization Techniques Employed in the IBM PowerPC 4xx Embedded Controllers, ISLPED, 1995, pp. 75–80.
Jun Chao, Yixin Zhao, Zhijun Wang, et al. Low-power implementations of DSP through operand isolation and clock gating. IEEE, 2007.
N. Banerjee, A. Raychowdhury, K. Rey, et al. Novel Low-overhead Operand Isolation Techniques for Low-Power Datapath Synthesis. IEEE, 2006.
Qing Wu, Massoud Pedram, and Xunwei Wu. Clock-gating and its application to low power design of sequential circuits. IEEE, 2000.
Michael De Nil, Lennart Yseboodt, Frank Bouwens. Ultra Low Power ASIP Design for Wireless Sensor Nodes. IEEE, 2007.
Kaijian Shim, David Howard. Challenges in sleep transistor design and implementation in low-power designs. DAC 2006, San Francisco, California, USA, July 24–28, 2006.
Arne Martin Holberg, Asmund Saetre. Innovative Techniques for Extremely Low Power Consumption with 8-bit Microcontrollers. Atmel Corporation White Paper, 2006.
Nariman Moezzi Madani, Naser Masoumi. A new optimization method for CTMDP system-level power management techniques. IEEE, 2004.
Manoj Kumar Jain, M. Balakrishnan, Anshul Kumar. ASIP Design Methodologies: Survey and Issues. In Int. Conf. on VLSI Design, Jan. 2001.
Tilman Glökler, Heinrich Meyr. Design of Energy-efficient Application Specific Instruction Set Processors, 2004, Kluwer Academic Publishers.
M. Hohenauer, H. Scharwaechter, K. Karuri, O. Wahlen. A methodology and tool suite for C compiler generation from ADL processor models. In Proceedings of the Conference on Design, Automation & Test in Europe (DATE), 2004.
Tensilica Inc.: http://www.tensilica.com.
CoWare Inc.: LISATek product family, http://www.coware.com.
Dake Liu. Embedded DSP Processor Design, 2008.
J. Henkel, S. Parameswaran. Designing Embedded Processors: A Low Power Perspective, 2007, Springer Publisher.
VIVEK TIWARI, SHARAD MALIK, ANDREW WOLFE. Instruction Level Power Analysis and Optimization of Software. Journal of VLSI Signal Processing.1996.
Paul Eric Landman. Low-Power Architectural Design Methodologies. 1994. pp. 63–68.
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Chen, L., Hei, Y., Yu, Z., Yuan, J., Xue, J. (2014). Low Power Design Methodologies for Digital Signal Processors. In: Tan, N., Li, D., Wang, Z. (eds) Ultra-Low Power Integrated Circuit Design. Analog Circuits and Signal Processing, vol 85. Springer, New York, NY. https://doi.org/10.1007/978-1-4419-9973-3_5
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